From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F10153398A; Mon, 5 Jan 2026 19:16:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767640595; cv=none; b=cGB4gjHYwNaKlQAispFEVtJmOj6RbJAZtUSrkdOZr/1l6q92XQaGq0n0iF74/GWQ3DbErTI+HveinF4i1xxqZ9HhZC3qbPHHylyYcd6gpc9b/woUIV6C9xfbGRCy28cNNKE8yuMOlWCRYL2lNc4HCGaGf1ZgRrpirid70HMwCCo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767640595; c=relaxed/simple; bh=povE5y5MY7Uwze3qy6H5gHZ1SQ221k5BK3sT4JoYWGs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=k8bxjuZBgwk0KnDEfDGXQJmetAsqLyQGNXSwU/qJEI6pD2O1TA7N5OQNI36wI3gAAsiDv2gLKD63yHgk0rYSawIIBjCbZHFMRZbYluDlN0ihSoEm4eq2Q7LAG+5GX6C/kFTDa+I3nnS+zGEKX3Z6dx0mHR3lAtUUteqRwWsBCLQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZLilpzwu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZLilpzwu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1EB85C116D0; Mon, 5 Jan 2026 19:16:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1767640594; bh=povE5y5MY7Uwze3qy6H5gHZ1SQ221k5BK3sT4JoYWGs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZLilpzwuyqmHP8n/r5pXfEADIgh+en0I5Bz/Oqta/W9EVsmck2dKAAnlGrWTJ5Olq Fo7saD73xUX6XAK5tMtR0fgkYgamXHid3fkt+YSw8kQnWqtqQ0l3Y4w6We6TqbQWkE rXYEUpt2hdNs/7141RHssAmVmxGpeP48gTA9gHRNKvTz8nX5oFBi4FIGGd0LKe5zeA u3iDPdRCfPkH3fq+FpaeuLR92EGa8cYD4ZcmLdjoiLUibaylMFFaYBaPgOsHh8s6eW ZgR0IhX7iNCDEH8IApQa9xI1fIgwQglQvrAyJF3I2zs59vOGoeblzEdeh0NhEaPeef hJf27d+Y2vpDw== From: Bjorn Andersson To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Konrad Dybcio , Sibi Sankar , Rajendra Nayak , Abel Vesa Cc: Neil Armstrong , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Abel Vesa , stable@vger.kernel.org, Dmitry Baryshkov Subject: Re: [PATCH RESEND v5 0/3] phy: qcom: edp: Add missing ref clock to x1e80100 Date: Mon, 5 Jan 2026 13:16:15 -0600 Message-ID: <176764058412.2961867.5718279320057221936.b4-ty@kernel.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251224-phy-qcom-edp-add-missing-refclk-v5-0-3f45d349b5ac@oss.qualcomm.com> References: <20251224-phy-qcom-edp-add-missing-refclk-v5-0-3f45d349b5ac@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Wed, 24 Dec 2025 12:53:26 +0200, Abel Vesa wrote: > According to documentation, the DP PHY on x1e80100 has another clock > called ref. > > The current X Elite devices supported upstream work fine without this > clock, because the boot firmware leaves this clock enabled. But we should > not rely on that. Also, when it comes to power management, this clock > needs to be also disabled on suspend. So even though this change breaks > the ABI, it is needed in order to make we disable this clock on runtime > PM, when that is going to be enabled in the driver. > > [...] Applied, thanks! [1/3] dt-bindings: phy: qcom-edp: Add missing clock for X Elite (no commit info) [2/3] phy: qcom: edp: Make the number of clocks flexible (no commit info) [3/3] arm64: dts: qcom: x1e80100: Add missing TCSR ref clock to the DP PHYs commit: 0907cab01ff9746ecf08592edd9bd85d2636be58 Best regards, -- Bjorn Andersson