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Fri, 16 Jan 2026 05:25:33 -0800 (PST) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Andersson , Wenbin Yao Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, Prudhvi Yarlagadda , Dmitry Baryshkov In-Reply-To: <20250825-glymur_pcie5-v3-0-5c1d1730c16f@oss.qualcomm.com> References: <20250825-glymur_pcie5-v3-0-5c1d1730c16f@oss.qualcomm.com> Subject: Re: (subset) [PATCH v3 0/4] PCI: qcom: Add support for Glymur PCIe Gen5x4 Message-Id: <176856992835.23711.2150005271893614146.b4-ty@kernel.org> Date: Fri, 16 Jan 2026 18:55:28 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=FscIPmrq c=1 sm=1 tr=0 ts=696a3c51 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=extm9pdXzRddJ-xlDaQA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-ORIG-GUID: htd3sT7INeqqvOUv5VzVaXFL5FH1UdB5 X-Proofpoint-GUID: htd3sT7INeqqvOUv5VzVaXFL5FH1UdB5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE2MDA5NCBTYWx0ZWRfX5UTLPjxYpVXK k76CjIxmP0rRmhPQAFh1pjXU4Flm/Sstn9JMosBlDKrua/v2DBRXY/lUHGwWQWaLc93QFY8PqAh fSv/FE6ZyLIeQHXne622WUkMn3mba2+c86U5S/baDrrv65nHY39rwfMEvHHABCbQbjmRqwOyYO/ NbVGa2CoDPx+UTemuxeT+7XSMKTy46TEwJew9YLMXfaRqxLgYwh3QAiLOO/KGtI2q7z+v7rqOla RRAHMnzZEjpkD3EPFUaeXGwU6hZBuR7WsUuCuanpVKC8gK5okxNVsx7GXWw8DifqoU+YQO1TmpW D5QLnCu4B0FTzF9rXiIpg4RhThuKCQljHoDPaf8FjWwf4SoMjDq0eaeZ4SkId4rw6OQ/t39KvbQ 5215T6390evia/jp/AeDpN+YDfvnDXTTq8YQqaBqKcbOJrWGCHODzpxCzT/fa50XF1UF4ICBENp Eq0yxJ/+pUiF48X4H5A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-16_05,2026-01-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 suspectscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601160094 On Mon, 25 Aug 2025 23:01:46 -0700, Wenbin Yao wrote: > Glymur is the next generation compute SoC of Qualcomm. This patch series > aims to add support for the fifth PCIe instance on it. The fifth PCIe > instance on Glymur has a Gen5 4-lane PHY. Patch [1/4] documents PHY as a > separate compatible and Patch [2/4] documents controller as a separate > compatible. Patch [3/4] describles the new PCS offsets in a dedicated > header file. Patch [4/4] adds configuration and compatible for PHY. > > [...] Applied, thanks! [2/4] dt-bindings: PCI: qcom: Document the Glymur PCIe Controller commit: e74887035fba99ead63235740908debeb1326dad Best regards, -- Manivannan Sadhasivam