From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E3A8329C7D; Fri, 23 Jan 2026 14:29:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769178576; cv=none; b=ULLCZ2F4wRDhqBZhXn9PLwkBMFj8tZ1khRGpjL7TNFkL+Sf+GR9wtRkhUPdkjLqMOZ0C9EYOW+FKPDH5LrvKq6Q9uh+Xunx5+Hc8obKZ3RRB3v9U5cJQgdd84aU+pj0Er1pD++UwxhFzqcfZbsasl6aHmtJ4XRcZ23ATbjJzDp8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769178576; c=relaxed/simple; bh=P+ugFIld2IJpYkF/9G+VgUVT0rklbLE22NNvUqHjN0Y=; h=From:Date:Content-Type:MIME-Version:Cc:To:In-Reply-To:References: Message-Id:Subject; b=DY87SgtBjCHZyRJ2i0ZtV68zwCRo5fcEaVvYvJ1zZXsO47t/OjtENEA8mjlM6PpOtfWZ6cVFxPXpHlHMSyj/GLkH+YivGFlCCG0owSmgm1wGcScBJITMzFE5SMyi74EGLkALRt427vacHLy4bHjSJI8t5ilN6VZncdI6mpO04eg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RVpfOEP/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RVpfOEP/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C6C43C19422; Fri, 23 Jan 2026 14:29:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769178575; bh=P+ugFIld2IJpYkF/9G+VgUVT0rklbLE22NNvUqHjN0Y=; h=From:Date:Cc:To:In-Reply-To:References:Subject:From; b=RVpfOEP/nmE2CUPbgdPdFnK3zNx2VJUyKnXm8zFhZVH9sxdRlsVtTzGnD6qqmD53B CT4Esmr2uNhFU42SLK79RY8ZqGdx2CSdQ2DKyQyWTkwflKmPXL3Jfxa9qWrkxX8ykV T/CVgNo/wL4qv5Gn1xssP0eE6Ea2mFSVZrvZP88RO3h4QR5xsCIkbRRusSdoXH55wx 6OncInwJx3K0YJV6DUlBnxkExepZytRONX/P3x8lKsMDUWMi+LzzWpTt7vTKwrFQb5 GjpxjpaolmC4IIR22oluqKEvFVsBWFngKepZ6HqIerYDFiXuHCV9Nus4OEYHU/hnPh UmWTMJ3r3sqQQ== From: Rob Herring Date: Fri, 23 Jan 2026 08:29:35 -0600 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Cc: Tingwei Zhang , linux-arm-msm@vger.kernel.org, Bjorn Andersson , Conor Dooley , linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org, Konrad Dybcio To: Jie Gan In-Reply-To: <20260123-enable-etr-and-ctcu-devices-v1-1-5fbb3423a2d7@oss.qualcomm.com> References: <20260123-enable-etr-and-ctcu-devices-v1-1-5fbb3423a2d7@oss.qualcomm.com> Message-Id: <176917840185.2044151.8624555547965761091.robh@kernel.org> Subject: Re: [PATCH] arm64: dts: qcom: talos: add ETR device On Fri, 23 Jan 2026 15:10:46 +0800, Jie Gan wrote: > Add the TMC ETR device to store collected trace data in DDR memory. > > Signed-off-by: Jie Gan > --- > arch/arm64/boot/dts/qcom/talos.dtsi | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade This patch series was applied (using b4) to base: Base: a0c666c25aeefd16f4b088c6549a6fb6b65a8a1d (use --merge-base to override) If this is not the correct base, please add 'base-commit' tag (or use b4 which does this automatically) New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20260123-enable-etr-and-ctcu-devices-v1-1-5fbb3423a2d7@oss.qualcomm.com: arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@100000 (qcom,qcs615-gcc): 'clock-names' is a required property from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml