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Tue, 03 Mar 2026 22:49:05 -0800 (PST) Received: from [192.168.1.2] ([2401:4900:88da:227d:6548:57ab:a3a:47f6]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82739dabd43sm21015522b3a.25.2026.03.03.22.48.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2026 22:49:04 -0800 (PST) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Niklas Cassel , Shawn Lin , Hans Zhang <18255117159@163.com>, Nicolas Frattaroli , Wilfred Mallawa , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Anand Moon Cc: Grimmauld In-Reply-To: <20260226101032.1042-1-linux.amoon@gmail.com> References: <20260226101032.1042-1-linux.amoon@gmail.com> Subject: Re: [PATCH v3] PCI: dw-rockchip: Enable async probe by default Message-Id: <177260693908.10259.13055467642416391434.b4-ty@kernel.org> Date: Wed, 04 Mar 2026 12:18:59 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=AJS1/0o2 c=1 sm=1 tr=0 ts=69a7d5e2 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=VwQbUJbxAAAA:8 a=SMwnmUEIIvgHDjHqlWcA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: lYpZapec9kQXm4qtGVYYtIchmzUpNfqV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA0MDA1MyBTYWx0ZWRfX02KFDU4fyP5L SpyOlED6wLXU9YHtcmxah365k+VWIcgS9TejPJ6H2qtOKHV3Xvvs489KDnGo8cz0GzwGhFo70Jz maf/FBhW6BM7dPaVNmsxd+gtitbmp6kwef3j6u7sIEpuzh/MCPDWHSzYjK60UjeuD9NFl5p+JBI /jm4PlCkwz0IynAqA44JgjOFvaIcUNvZx0uhkM4AOLyO/7izS37EMrmtT/LeRhzmeZ1NClOETRU ClMKB6pPGKcb1ovfrGNj4ZkElx3sRfjr+beCPIxqdqj143frD+rqEH0DDaDZi2sfYmXrK7c7NGq GtPRG3rXFfiFGKAMy3XqgX03GDjnI9oZv/NePFRFMbGV/s4s+UR9PGWc+mV7vrgWQalt3efGLJV RP6s1a8QyDWM3oCl0ax0IAfxdONbGtodXKE75vqtwKI3s2m/3RJ4/EQUcARNbEWgN/oViIMrPnV MBfEPCJTSjQ3ylQNFGw== X-Proofpoint-GUID: lYpZapec9kQXm4qtGVYYtIchmzUpNfqV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-04_02,2026-03-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 spamscore=0 phishscore=0 adultscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603040053 On Thu, 26 Feb 2026 15:40:23 +0530, Anand Moon wrote: > Rockchip DWC PCIe driver currently performs synchronous link training for > combo PHYs (PCIe 3.0/2.0 and SATA 3.0) during boot. This process waits for > the link to be fully established, adding several milliseconds to the boot > sequence. To optimize boot time, this change enables asynchronous probing, > allowing link establishment to proceed in the background while the kernel > continues probing other devices. > > [...] Applied, thanks! [1/1] PCI: dw-rockchip: Enable async probe by default commit: ec392abc95932838bf7e3d659d358f4df9ff5a0a Best regards, -- Manivannan Sadhasivam