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b=Dsl0oNc7yQ90ZB/jOhFKwLEPIMvk140THuV680QUX8j7Mqb7JIm5GnwYErqRTpaq9BkffqqqXqG4jPP0NWioCxG4VZc7lthbF4ozSqusIRssC4OGZkUG3g5Ofn87KTuIeR330J/VFBVzNikY1U/BrYoxG6XaUbSnFkxIT1eaJNw2n32MsjoXDvHlvKmyxHI1lZ+Wc36OipVQTiUyL4xJOBRZil9fhGN+FHE4hlCVtAmuZKT+zLwShtOABJ8jLFM5GeByfhFVGPlokspVHbmM/R2jJVWD8g4anWy8MB+bnt3whqI/bnausH1dV6FexaV3boRpY5fj1+4+rfqNswJC0Q== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) by DM4PR12MB5867.namprd12.prod.outlook.com (2603:10b6:8:66::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9769.11; Mon, 30 Mar 2026 02:24:13 +0000 Received: from SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017]) by SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017%4]) with mapi id 15.20.9769.006; Mon, 30 Mar 2026 02:24:13 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: Re: [PATCH v2 4/7] pwm: tegra: Parametrize enable register offset From: Mikko Perttunen To: Thierry Reding Cc: Mikko Perttunen , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Hunter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Yi-Wei Wang In-Reply-To: References: <20260325-t264-pwm-v2-0-998d885984b3@nvidia.com> <20260325-t264-pwm-v2-4-998d885984b3@nvidia.com> Date: Mon, 30 Mar 2026 11:24:09 +0900 Message-Id: <177483744958.916245.860145469758840098.b4-reply@b4> X-Mailer: b4 0.16-dev-ad80c X-ClientProxiedBy: TYCP286CA0239.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:3c7::17) To SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR12MB9161:EE_|DM4PR12MB5867:EE_ X-MS-Office365-Filtering-Correlation-Id: a89064ac-80d6-4003-d4d7-08de8e036ec7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|10070799003|376014|7416014|22082099003|18002099003|56012099003; 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Hence, introduce an enablement offset field in > > the tegra_pwm_soc structure to describe the offset of the register. > > > > Co-developed-by: Yi-Wei Wang > > Signed-off-by: Yi-Wei Wang > > Signed-off-by: Mikko Perttunen > > --- > > drivers/pwm/pwm-tegra.c | 17 ++++++++++++----- > > 1 file changed, 12 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c > > index cf54f75d92a5..22d709986e8c 100644 > > --- a/drivers/pwm/pwm-tegra.c > > +++ b/drivers/pwm/pwm-tegra.c > > @@ -61,6 +61,7 @@ > > > > struct tegra_pwm_soc { > > unsigned int num_channels; > > + unsigned int enable_reg; > > }; > > > > struct tegra_pwm_chip { > > @@ -197,8 +198,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, > > err = pm_runtime_resume_and_get(pwmchip_parent(chip)); > > if (err) > > return err; > > - } else > > + } else if (pc->soc->enable_reg == PWM_CSR_0) { > > val |= PWM_ENABLE; > > + } > > This looks incomplete for the Tegra264 case where > > pc->soc->enable_reg == PWM_CSR_1 > > > > > pwm_writel(pwm, PWM_CSR_0, val); > > I think we need another write for PWM_CSR_1 here to properly toggle the > PWM_ENABLE bit on Tegra264. > > Or am I missing something? This check is here just so we don't change the value of PWM_ENABLE when writing the CSR_0 register. The function doesn't write to CSR_1 so nothing needs to be done on Tegra264. I agree it's not the clearest, but it'll get cleaned up when adding support for configurable depth, as at that point we will need to write both registers on Tegra264. > > Thierry