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Tue, 12 May 2026 04:20:15 -0700 (PDT) Received: from [192.168.1.102] ([120.56.206.29]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965b333f2sm28587654b3a.20.2026.05.12.04.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2026 04:20:15 -0700 (PDT) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jian Yang Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, chuanjia.liu@mediatek.com, yonglong.wu@mediatek.com In-Reply-To: <20260413071401.1151-1-jian.yang@mediatek.com> References: <20260413071401.1151-1-jian.yang@mediatek.com> Subject: Re: [PATCH 0/2] PCI: mediatek-gen3: Fix the control timing of PERST# Message-Id: <177858481069.17084.1434409769087889023.b4-ty@b4> Date: Tue, 12 May 2026 16:50:10 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailer: b4 0.15.0 X-Authority-Analysis: v=2.4 cv=IsAutr/g c=1 sm=1 tr=0 ts=6a030cf1 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=QuRtzvr4xB5J0le8HPcEzQ==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=VwQbUJbxAAAA:8 a=bPlxViFAvYB88tiJ6gEA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: 63HRzjHqD2mg778xvOewwTtAYCYAehf9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEyMDExNyBTYWx0ZWRfX2v8nOeQKyul9 mrXN9XATSBmq8Kn+08b07g6xdWo2QTLfaSCZSC5I9ZvSWt3xTMISn+WVF6WDCP72iLgKdBBFFny 1qt9JyipvpoWfY6JMFrVeJtAIFf2jAHCDojf7fygu/F1VEUeefq6aTFXwzz1u27nllqi/HnxuB2 wvzSlOd6zIJ2g2yz1L9qanuOqhWDbCGL5AkmuE+NaivPTlAfJYc5Y0wcKADf3LYlDEpZgcuSK7O CGUYMpafZRrFI7CcBgrul41GeSMMWScpB1gf4Nlo5PR8safsK3Y9NUdgqIV0oXxONLFH/SS+DsC PcAQXnkYN5Qm+I0R5NoAcWth6KJzE2qpfTs4bVbafNBB1VHNQ+rqSKYpnqDjFvj8EvtI8xdKUrj VchM/Gcqh56qZbJDtf+DQAn2zYh/OtK9zlKN2zRo3HJLWQVsYT+uLZ3l2eKypd2KGhsxjJCrnSY ofxxTPza2aFYletwR/g== X-Proofpoint-ORIG-GUID: 63HRzjHqD2mg778xvOewwTtAYCYAehf9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-11_05,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 bulkscore=0 clxscore=1015 phishscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605120117 On Mon, 13 Apr 2026 15:13:54 +0800, Jian Yang wrote: > The purpose of this patch series is to fix the PERST# control timing > in the MediaTek PCIe Gen3 controller driver so that it complies with > the PCIe CEM specification. > > In the current MediaTek PCIe Gen3 controller driver, there are two > issues with PERST# timing: > 1. During the power-up phase (i.e., before PCIe link-up), on some > MediaTek SoCs PERST# is de-asserted before the REFCLK becomes stable; > 2. During system shutdown, PERST# is not asserted before power is > removed. > > [...] Applied, thanks! [1/2] PCI: mediatek-gen3: Fix PERST# control timing during system startup commit: bcc32882066156029e1e9ea16a3c3b8f3100cc3d [2/2] PCI: mediatek-gen3: Add a shutdown callback to cotnrol PERST# signal commit: c019c3ad821ec38ee158cda4be5ab8e39d2d5c6b Best regards, -- Manivannan Sadhasivam