From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E9743EA978 for ; Tue, 19 May 2026 15:24:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779204261; cv=none; b=h7c6siaCGqFI9lNGkIAkadMmftfzN1gVdvBj0i2fM8Newx40P0ahTp+gp6TZYdbseleDdvsMe1cfG1/PG+EnfvSDheygZl8DeWdjaQXXAB+ryPpjhhv+0g7LgOUU424OrrI/uewhSIyfOrCkACp5e9uqNei5l2GGtlQpYHbtmv8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779204261; c=relaxed/simple; bh=g6wFFESjTSNXvwgWRPzOHxgpnotAl76JdKDkRbi+4R8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HVMB9fhqQHaguTwvEelKP1ssbJkQginnRdpepbVg0c9Rbp0W6xRY+A6FDCV7TCwn9UHr2k1xmcOZyZFCkWmOGpb5jDaNUA7FTT6aWwp/Al2dDdoM7L4ASFu3dvYqr5OrMqe8te4E0wbMv8yYXUB2pNA/4HKhTVOTN4NBG99Dv9U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CWFjMppI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CWFjMppI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DE9AC2BCB3; Tue, 19 May 2026 15:24:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779204261; bh=g6wFFESjTSNXvwgWRPzOHxgpnotAl76JdKDkRbi+4R8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CWFjMppIquo3NagmRnyMy9vO9YkLJ8XlntsvQaJ0TA65U7XJY17dfQEvJMIK7DYiI Kt7IE9gtQ+0w/dEnhXvSnX+j2Cm52HSDuOJOx9eZUueCQeDLmSoFE+/0ixgxFu0gwk bL9R7Ka3NkwKe+2FV+Bt+ed0SLZO3HrOZPTf8uUuhUi9aFsMz9cadGBJqKMdfRJiMl Xws10vXKsJ6/UdYoJyUd9LLjLrOFMEUomdONxfEd85FhvW5N6LjEjR1mn5Sd8bp+ET DuMoWyCX9ql5BQSheWk1dRFqSJFKnnM98EuQ0xIZ4rba74EGF8p2gPT2k8JTRrjIae sU4tmVfFf7j3A== From: Will Deacon To: Catalin Marinas , Ard Biesheuvel , Ryo Takakura , Breno Leitao , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Osama Abdelkader Cc: kernel-team@android.com, Will Deacon Subject: Re: [PATCH v2] arm64: panic from init_IRQ if IRQ handler stacks cannot be allocated Date: Tue, 19 May 2026 16:23:08 +0100 Message-ID: <177919003152.809113.14381397697687715929.b4-ty@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260326225755.50297-1-osama.abdelkader@gmail.com> References: <20260326225755.50297-1-osama.abdelkader@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Thu, 26 Mar 2026 23:57:52 +0100, Osama Abdelkader wrote: > init_irq_stacks() and init_irq_scs() may fail when arch_alloc_vmap_stack > or scs_alloc return NULL. Return -ENOMEM from both and call panic() once > from init_IRQ(), covering per-CPU IRQ stacks and shadow IRQ stacks > consistently. > > Applied to arm64 (for-next/misc), thanks! [1/1] arm64: panic from init_IRQ if IRQ handler stacks cannot be allocated https://git.kernel.org/arm64/c/7dc6922f7fdd Cheers, -- Will https://fixes.arm64.dev https://next.arm64.dev https://will.arm64.dev