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Tue, 19 May 2026 07:17:57 -0700 (PDT) Received: from [192.168.1.11] ([120.56.207.212]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bd5cfe492asm194269575ad.48.2026.05.19.07.17.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2026 07:17:57 -0700 (PDT) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, Frank.Li@nxp.com, den@valinux.co.jp, hongxing.zhu@nxp.com, jingoohan1@gmail.com, vidyas@nvidia.com, cassel@kernel.org, 18255117159@163.com, Manikanta Maddireddy Cc: linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260515070753.3852840-1-mmaddireddy@nvidia.com> References: <20260515070753.3852840-1-mmaddireddy@nvidia.com> Subject: Re: (subset) [PATCH v3 0/2] PCI: tegra194: ASPM L1 entrance latency from device tree Message-Id: <177920027083.95581.15850589651650964424.b4-ty@kernel.org> Date: Tue, 19 May 2026 19:47:50 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=JKULdcKb c=1 sm=1 tr=0 ts=6a0c7117 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=1gRTTRxgmbTSdBvl+srOOw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=VwQbUJbxAAAA:8 a=H5kH8eP05ZJGUFTVoxsA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: 4J_Bg_QMfyRo901w9avpr5fI5oSi9if3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDE0MiBTYWx0ZWRfX7bl00yJ2MGNA qW85CqCqcm7j4y2R4tx68QX/izK8w/JSLjGtHUFYBhA/udidfMJh4WGUMx5/C059itsNs1JHU+5 uuzBtfg/dFEr3mnbC/YG4UHzfuX1Hhh/XsXl+GUTEF+qXtFO0Z2KByhIBMdJSgBBmk+HXbu+2nb +HAYRFfYV+3pLT2HmNfZ2AvWx8uoENmtxdvl54xuPn8HiLzyzyEzvuUNNx0ysoPuQP5dBGP+On7 BCy2yC2H05KJcZ6q3kx44JbXFODVOM1SMBneYfNqCfgCSuz6FusbcOmrdrNmV8Pu005+/uBgyU6 a1X6xQMUDPZxz4Z+20rGZkCe24iB+TH52yP8ZCWWbRJsMFSpN7UyZGmXxrjb8fsD18Qx58qjktk 4D0hcU/mHIKHX5anKKUU6FRQNn/CNHo4hYi3I31whH7srA7EyMASMoT0oD0ssEbiREKJ5om1GVL XIBkf4S/F0Y5ftWucNA== X-Proofpoint-ORIG-GUID: 4J_Bg_QMfyRo901w9avpr5fI5oSi9if3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190142 On Fri, 15 May 2026 12:37:51 +0530, Manikanta Maddireddy wrote: > This series programs Synopsys DesignWare ASPM L1 entrance latency on NVIDIA > Tegra194/234 PCIe controllers from an optional device tree property and > corrects the default nanosecond cells so the PORT_AFR field advertises the > intended latency buckets. > > Background > ---------- > The controller exposes L1 entrance latency in PCI Express PORT_AFR (DW DBI), > bits 27:29. Software must select a 3-bit code for the maximum L1 entry delay > the platform can tolerate. Patch 1 reads aspm-l1-entry-delay-ns (nanoseconds), > converts to whole microseconds with ceiling division (DIV_ROUND_UP), and > programs min(order_base_2(us), 7) into PORT_AFR during ASPM init. If the > property is absent, the driver keeps the existing default (code 7). > > [...] Applied, thanks! [1/2] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency commit: 87f493041e20759ffc27262cc0490c41628a5ee2 Best regards, -- Manivannan Sadhasivam