mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: "tip-bot2 for Tianyang Zhang" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Tianyang Zhang <zhangtianyang@loongson.cn>,
	Thomas Gleixner <tglx@kernel.org>,
	Huacai Chen <chenhuacai@loongson.cn>,
	x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: irq/drivers] Docs/LoongArch: Add advanced extended IRQ model
Date: Wed, 03 Jun 2026 20:32:29 -0000	[thread overview]
Message-ID: <178051874920.710.6070236161445226440.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20260513012839.2856463-2-zhangtianyang@loongson.cn>

The following commit has been merged into the irq/drivers branch of tip:

Commit-ID:     89bb21e9b57defa9a33ff01020d44f3fd6802026
Gitweb:        https://git.kernel.org/tip/89bb21e9b57defa9a33ff01020d44f3fd6802026
Author:        Tianyang Zhang <zhangtianyang@loongson.cn>
AuthorDate:    Wed, 13 May 2026 09:28:32 +08:00
Committer:     Thomas Gleixner <tglx@kernel.org>
CommitterDate: Wed, 03 Jun 2026 22:28:11 +02:00

Docs/LoongArch: Add advanced extended IRQ model

Introduce a new advanced extended interrupt model with redirect interrupt
controllers. When the redirect interrupt controller is enabled, the routing
target of MSI interrupts is no longer a specific CPU and vector number, but
a specific redirect entry. The actual CPU and vector number used are
described by the redirect entry.

Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Acked-by: Huacai Chen <chenhuacai@loongson.cn>
Link: https://patch.msgid.link/20260513012839.2856463-2-zhangtianyang@loongson.cn
---
 Documentation/arch/loongarch/irq-chip-model.rst                    | 35 +++++++++++++++++++++++++++++++++++
 Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+)

diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rst
index 8f5c334..774d40d 100644
--- a/Documentation/arch/loongarch/irq-chip-model.rst
+++ b/Documentation/arch/loongarch/irq-chip-model.rst
@@ -181,6 +181,41 @@ go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::
              | Devices |
              +---------+
 
+Advanced Extended IRQ model (with redirection)
+==============================================
+
+In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
+to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
+to REDIRECT for remapping it to AVECINTC, and then go to CPUINTC directly, while
+all other devices interrupts go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and
+then go to CPUINTC directly::
+
+ +-----+     +-----------------------+     +-------+
+ | IPI | --> |        CPUINTC        | <-- | Timer |
+ +-----+     +-----------------------+     +-------+
+              ^          ^          ^
+              |          |          |
+              |    +----------+     |
+       +---------+ | AVECINTC | +---------+     +-------+
+       | EIOINTC | +----------+ | LIOINTC | <-- | UARTs |
+       +---------+ | REDIRECT | +---------+     +-------+
+            ^      +----------+
+            |            ^
+            |            |
+       +---------+  +---------+
+       | PCH-PIC |  | PCH-MSI |
+       +---------+  +---------+
+         ^     ^           ^
+         |     |           |
+ +---------+ +---------+ +---------+
+ | Devices | | PCH-LPC | | Devices |
+ +---------+ +---------+ +---------+
+                  ^
+                  |
+             +---------+
+             | Devices |
+             +---------+
+
 ACPI-related definitions
 ========================
 
diff --git a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst
index d4ff80d..87b58ae 100644
--- a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst
+++ b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst
@@ -174,6 +174,40 @@ CPU串口(UARTs)中断发送到LIOINTC,PCH-MSI中断发送到AVECINTC,
              | Devices |
              +---------+
 
+高级扩展IRQ模型 (带重定向)
+==========================
+
+在这种模型里面,IPI(Inter-Processor Interrupt)和CPU本地时钟中断直接发送到CPUINTC,
+CPU串口(UARTs)中断发送到LIOINTC,PCH-MSI中断首先发送到REDIRECT模块,完成重定向后发
+送到AVECINTC,而后通过AVECINTC直接送达CPUINTC,而其他所有设备的中断则分别发送到所连
+接的PCH-PIC/PCH-LPC,然后由EIOINTC统一收集,再直接到达CPUINTC::
+
+ +-----+     +-----------------------+     +-------+
+ | IPI | --> |        CPUINTC        | <-- | Timer |
+ +-----+     +-----------------------+     +-------+
+              ^          ^          ^
+              |          |          |
+              |    +----------+     |
+       +---------+ | AVECINTC | +---------+     +-------+
+       | EIOINTC | +----------+ | LIOINTC | <-- | UARTs |
+       +---------+ | REDIRECT | +---------+     +-------+
+            ^      +----------+
+            |            ^
+            |            |
+       +---------+  +---------+
+       | PCH-PIC |  | PCH-MSI |
+       +---------+  +---------+
+         ^     ^           ^
+         |     |           |
+ +---------+ +---------+ +---------+
+ | Devices | | PCH-LPC | | Devices |
+ +---------+ +---------+ +---------+
+                  ^
+                  |
+             +---------+
+             | Devices |
+             +---------+
+
 ACPI相关的定义
 ==============
 

  reply	other threads:[~2026-06-03 20:32 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-13  1:28 [PATCH v12 0/4] Loongarch irq-redirect support Tianyang Zhang
2026-05-13  1:28 ` [PATCH v12 1/4] Docs/LoongArch: Add advanced extended IRQ model (redirection) description Tianyang Zhang
2026-06-03 20:32   ` tip-bot2 for Tianyang Zhang [this message]
2026-05-13  1:28 ` [PATCH v12 2/4] irqchip/loongarch-avec: Prepare for interrupt redirection support Tianyang Zhang
2026-06-03 20:32   ` [tip: irq/drivers] " tip-bot2 for Tianyang Zhang
2026-05-13  1:28 ` [PATCH v12 3/4] irqchip/loongarch-avec: Return IRQ_SET_MASK_OK_DONE when keep affinity Tianyang Zhang
2026-06-03 20:32   ` [tip: irq/drivers] " tip-bot2 for Tianyang Zhang
2026-05-13  1:28 ` [PATCH v12 4/4] irqchip/loongarch-ir: Add IR (interrupt redirection) irqchip support Tianyang Zhang
2026-06-03 20:32   ` [tip: irq/drivers] " tip-bot2 for Tianyang Zhang
2026-05-13  2:50 ` [PATCH v12 0/4] Loongarch irq-redirect support Huacai Chen

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=178051874920.710.6070236161445226440.tip-bot2@tip-bot2 \
    --to=tip-bot2@linutronix.de \
    --cc=chenhuacai@loongson.cn \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-tip-commits@vger.kernel.org \
    --cc=tglx@kernel.org \
    --cc=x86@kernel.org \
    --cc=zhangtianyang@loongson.cn \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®