From: Vinod Koul <vkoul@kernel.org>
To: ldewangan@nvidia.com, jonathanh@nvidia.com,
akhilrajeev@nvidia.com, Frank.Li@kernel.org,
thierry.reding@kernel.org, digetx@gmail.com,
pkunapuli@nvidia.com, dmaengine@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
Kartik Rajput <kkartik@nvidia.com>
Cc: stable@vger.kernel.org, Frank Li <Frank.Li@nxp.com>
Subject: Re: [PATCH RESEND] dmaengine: tegra: Fix burst size calculation
Date: Mon, 08 Jun 2026 17:44:00 +0530 [thread overview]
Message-ID: <178092084039.97019.1123733589593196697.b4-ty@kernel.org> (raw)
In-Reply-To: <20260422064134.1323610-1-kkartik@nvidia.com>
On Wed, 22 Apr 2026 12:11:34 +0530, Kartik Rajput wrote:
> Currently, the Tegra GPC DMA hardware requires the transfer length to
> be a multiple of the max burst size configured for the channel. When a
> client requests a transfer where the length is not evenly divisible by
> the configured max burst size, the DMA hangs with partial burst at
> the end.
>
> Fix this by reducing the burst size to the largest power-of-2 value
> that evenly divides the transfer length. For example, a 40-byte
> transfer with a 16-byte max burst will now use an 8-byte burst
> (40 / 8 = 5 complete bursts) instead of causing a hang.
>
> [...]
Applied, thanks!
[1/1] dmaengine: tegra: Fix burst size calculation
commit: 4651df83b6c796daead3447e8fd874322918ee4f
Best regards,
--
~Vinod
prev parent reply other threads:[~2026-06-08 12:14 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-22 6:41 Kartik Rajput
2026-04-22 9:26 ` Jon Hunter
2026-06-08 6:22 ` Kartik Rajput
2026-06-08 12:14 ` Vinod Koul [this message]
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