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Tue, 09 Jun 2026 08:25:43 -0700 (PDT) Received: from [192.168.1.11] ([120.56.203.186]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84282880050sm21250746b3a.29.2026.06.09.08.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2026 08:25:42 -0700 (PDT) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, vigneshr@ti.com, jingoohan1@gmail.com, thomas.petazzoni@bootlin.com, ryder.lee@mediatek.com, claudiu.beznea.uj@bp.renesas.com, mpillai@cadence.com, Hans Zhang <18255117159@163.com> Cc: robh@kernel.org, s-vadapalli@ti.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, claudiu.beznea@tuxon.dev, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260518004246.1384532-1-18255117159@163.com> References: <20260518004246.1384532-1-18255117159@163.com> Subject: Re: [PATCH v4 0/7] PCI: Add common helper for 100 ms delay after link training Message-Id: <178101873635.8877.10733384254725006435.b4-ty@kernel.org> Date: Tue, 09 Jun 2026 20:55:36 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA5MDE0NiBTYWx0ZWRfXz1B7Ddv0PzsD CGbOvgucqMJecAGpQ//0IiANIYbSez7rPQvNku6fTuHfXhIJTvtpi/l8Msw7pF/ga1SgiTHN5cZ IWCWNejZ7InJfMptvZC3p4F/paFUItAa88uapN1Sg4jYwlwyJRBBV/sduTBluh1gtafLoNuo8Ii vUy3P8MbpQ4tOw8XSYStppgMtbMdmmMYhyI57fkRsojcXMYrNrcumg6x2AyoU+hFx7s8p2zCxJC bMs10IFRGIcdDTtVPsadM4DS7aKoUB52DFKCXBr1ROfHhoStEUvKyPblUmptRsVJEQoj0GTeMcf v7osVCFXQDBQ5vAowezqvroexFmkUK2QgBIULXmlwJB1f20M5sk7/5mjFO0NB8I+j6FTeGtYu31 WjN1cQ2Byep2/czwnPu+MsTGqtB2J/nzH65UERR3EvE6+ym3ZdiBz0wLZBhc/ezWqbB8TF/TCmR jU+hJ0NKT+F29zl94Jg== X-Authority-Analysis: v=2.4 cv=csWrVV4i c=1 sm=1 tr=0 ts=6a283079 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=eDurORsI8St+1bJHqsJewQ==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=VwQbUJbxAAAA:8 a=snT30zDU7jmJpjBr2YoA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: -hA0bvuiGLbcCqPxF0_9HwkY0AkucsZq X-Proofpoint-ORIG-GUID: -hA0bvuiGLbcCqPxF0_9HwkY0AkucsZq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-09_03,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 phishscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606090146 On Mon, 18 May 2026 08:42:39 +0800, Hans Zhang wrote: > PCIe r6.0, sec 6.6.1 (Conventional Reset) requires that for a Downstream > Port supporting Link speeds greater than 5.0 GT/s, software must wait a > minimum of 100 ms after Link training completes before sending any > Configuration Request. > > Several PCIe host controller drivers currently omit this 100 ms delay > when the negotiated link speed is Gen3 (8 GT/s) or higher. Only the DWC > driver already implements it. The missing delay can lead to violations > of the PCIe specification and cause enumeration failures with high-speed > devices (e.g., NVIDIA RTX5070 GPU, PCIe 5.0 NVMe SSDs). > > [...] Applied, thanks! [1/7] PCI: Add pci_host_common_link_train_delay() helper commit: 29fbf582e75015c031e7965fdd4084af123b9ca2 [2/7] PCI: cadence: Add post-link delay for LGA and j721e glue driver commit: 869317b95fd735684057666a65dd8ef95d4bd669 [3/7] PCI: cadence: HPA: Add post-link delay commit: 8dd5d65d0dc750b6890c0102c3992f4cef516196 [4/7] PCI: dwc: Use common pci_host_common_link_train_delay() helper commit: 681adc339e4c972b9f7a5ef8c2fb6a2f7737d4db [5/7] PCI: aardvark: Add 100 ms delay after link training commit: 8a602b8bfebbf9a755e8f4732132719a3b298b29 [6/7] PCI: mediatek-gen3: Add 100 ms delay after link up commit: 798a96740d61c24f193b82388b681b6a4f102d3b [7/7] PCI: rzg3s-host: Use common pci_host_common_link_train_delay() helper commit: 0ae259d0434bc31fc71696355538fd21027d6ebe Best regards, -- Manivannan Sadhasivam