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Thu, 11 Jun 2026 00:20:58 -0700 (PDT) Received: from [192.168.1.11] ([120.56.195.233]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c24edc8ad7sm145922405ad.42.2026.06.11.00.20.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 00:20:57 -0700 (PDT) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: linux-pci@vger.kernel.org, Rosen Penev Cc: Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Lorenzo Pieralisi , linusw@kernel.org, =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org In-Reply-To: <20260526044016.1025613-1-rosenp@gmail.com> References: <20260526044016.1025613-1-rosenp@gmail.com> Subject: Re: [PATCHv2] PCI: mvebu: Use fixed-width interrupt masks Message-Id: <178116245413.8388.17772545908959484770.b4-ty@kernel.org> Date: Thu, 11 Jun 2026 12:50:54 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=PZPPQChd c=1 sm=1 tr=0 ts=6a2a61db cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=n8UK4BQKCdfH/t0JQ2luxA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=SiPLVwNLmWBdlGvAHpkA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: f6Mjv4TYQvYfzMuJ5hp8c_5KaNhQPLf4 X-Proofpoint-GUID: f6Mjv4TYQvYfzMuJ5hp8c_5KaNhQPLf4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjExMDA3MSBTYWx0ZWRfX+U8QmBtPc7CB ycU/6zsuMqpTEKrx1zenVpHPjPrZahQvHg3as90PjG/V5b2aLgO21MpncgDVOwOsc52KfPVaHDv su5r1I/lrJCRwBID3fF8BxvaF5yS39CW3NYrO4ZXaL+lM32AV060ZpW9H6wYmYCwkHl6AzujK3o AfCb4Cq6Bo8mo/RhDFPm7+n9A/gAqO6Xj50Z1tJefdVergZYP2f7t/Rs1+tWc9I2ZJKT8SQeAV0 9t5xxt92Yrza7BmK84Y1+ibDF0fg/p/9Kul3risHKGEfiPjn+dSIyp0caAEAegBZ/8HS+bFq1Os TEOSpuBQHKRxhOf5gXsyb4aH1pb5GHukhg8kOfPlm0fpDZdqOU9mUj6UDQPhrTi6oEnLnQR3x82 FInjdd5cd6z6UM/KLHxpcWYfVOtkHcfXjC1RMZ38y8wJZOwyJg93fdoYnZRrpLKtDTjFlaTu99B cLgQ6dWYjJHztcjkbfA== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjExMDA3MSBTYWx0ZWRfXx6+0kGIFl4sE ungwXmwgsZtucH1hfXo3v2/VOOvEGjiqMnEydNcjlkVcomvOZpbr2G71pwj6m9jE6CwDPXw0woy Az1izDvWb+rVKNX+k1/+6QQW+jkiZ2o= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-11_01,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 spamscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606110071 On Mon, 25 May 2026 21:40:16 -0700, Rosen Penev wrote: > Use u32-typed BIT and GENMASK helpers for PCIe interrupt register > masks. This keeps inverted masks in the same width as the registers > and avoids truncation warnings on 64-bit compile-test builds. > > Fixes this and similar warnings: > > drivers/pci/controller/pci-mvebu.c:316:21: error: implicit conversion from > 'unsigned long' to 'u32' (aka 'unsigned int') changes value from > 18446744069414584320 to 0 [-Werror,-Wconstant-conversion] > 316 | mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF); > > [...] Applied, thanks! [1/1] PCI: mvebu: Use fixed-width interrupt masks commit: c525508c1854e72b080b49e6ff7074913dc1905d Best regards, -- Manivannan Sadhasivam