From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C65930B53C; Thu, 11 Jun 2026 08:31:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781166706; cv=none; b=pnrQISSFIsYkTfNtCiljPNLl4J6OU6y17MrMobfmHQHATxcmrBfjUJjoKXy5usgX+3l06hlNycbrnlHtyWmiSZ4ztgcnka0fq5qJUkH+0fyzjo1h68Dhf9gwMnO9EwulIHM2fIS4zCy31bdBYHkae4m1oUNYUnuoXWLMvpGnEd4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781166706; c=relaxed/simple; bh=JJGlH8TP/tSJ7wDID1f/5vn9dRq9yiJqlGLpF+IaS2o=; h=Date:From:To:Subject:Cc:MIME-Version:Message-ID:Content-Type; b=akkJm6y19Db64x2NjTygWaLxe14x4FSep++ZbhZcseV2Ui+ayM8N8LDWuAfYZXclT1mhhX+a5tvNaVAYR+ZHpq9sP9/d61ZJFhCVBba3XoVMYc2zfO2ACUG1C7eJGozd486PRbotLRGCzA4Z9WwiXyjI2fqikvzh2nucduMlLnU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=wp6m697K; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=lRkca7ax; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="wp6m697K"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="lRkca7ax" Date: Thu, 11 Jun 2026 08:31:41 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1781166703; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=BFt+wdHqOO2v3GnRCp9Hyoo5gv12BLKP9Vk+bGTT+uk=; b=wp6m697KXcNuzt8oHGagryF7Q07+QLJ/lTb1D8qfL9NLj9HNNcjhLidrGelATRl3Gz7dWm 6Y4ed9/HIqzwb1J1Tv0r7VQ+4bfJawkjcnTl7OKjN5/W2f68CNq0BsPYOaJv45MC4f4Wea tsIz93AjX/MWLU23807opkMpDhcg9BJdPgMBs++ZPHUI9f6lr1VhlCiGWoULhSUcdNe6LU t1qZ5hpG+VncZk5MLjr3S16vUpsGoq7RKCvy7QBp9ycY9qDVzOc6WeXHHVkMnes4Dc4aTg RTPjUQkCSSIRc+goSpa+YboUfql/xCXQSJ8Qm8HHj/LCX+m1apvs0zlfpGP+HA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1781166703; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=BFt+wdHqOO2v3GnRCp9Hyoo5gv12BLKP9Vk+bGTT+uk=; b=lRkca7axEspuCZ0dwnEZRTUk8d48nBtboYZM2z3Mi1YxBx1OZagYOt+s7DPT+PTaM8eYrz SGod1Jbim3kR1BCA== From: "tip-bot2 for Ingo Molnar" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] x86/cpu: Remove unused !CONFIG_X86_TSC code Cc: Ingo Molnar , Arnd Bergmann , Dave Hansen , "Ahmed S . Darwish" , Andrew Cooper , Ard Biesheuvel , "H . Peter Anvin" , John Ogness , Linus Torvalds , Peter Zijlstra , x86@kernel.org, linux-kernel@vger.kernel.org Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178116670165.529383.6532474303063720366.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 5c75b98aa9cd5b1725b76999d794dc72ebd7a54a Gitweb: https://git.kernel.org/tip/5c75b98aa9cd5b1725b76999d794dc72ebd= 7a54a Author: Ingo Molnar AuthorDate: Mon, 27 Apr 2026 08:07:02 +02:00 Committer: Ingo Molnar CommitterDate: Thu, 11 Jun 2026 10:25:34 +02:00 x86/cpu: Remove unused !CONFIG_X86_TSC code Now that the Kconfig space always enables CONFIG_X86_TSC (on x86), remove !CONFIG_X86_TSC code from the x86 arch code. We still keep the Kconfig option to catch any eventual code still pending in maintainer or non-mainline trees, plus some drivers have raw TSC timestamping hacks that use CONFIG_X86_TSC. It's also still possible to disable TSC support runtime. Signed-off-by: Ingo Molnar Reviewed-by: Arnd Bergmann Acked-by: Dave Hansen Cc: Ahmed S . Darwish Cc: Andrew Cooper Cc: Ard Biesheuvel Cc: H . Peter Anvin Cc: John Ogness Cc: Linus Torvalds Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20250425084216.3913608-13-mingo@kernel.org --- arch/x86/include/asm/timex.h | 3 +-- arch/x86/include/asm/trace_clock.h | 8 -------- arch/x86/include/asm/tsc.h | 13 +------------ arch/x86/kernel/Makefile | 4 ++-- arch/x86/kernel/i8253.c | 2 +- arch/x86/kernel/tsc.c | 13 ------------- 6 files changed, 5 insertions(+), 38 deletions(-) diff --git a/arch/x86/include/asm/timex.h b/arch/x86/include/asm/timex.h index 956e414..6e57e3c 100644 --- a/arch/x86/include/asm/timex.h +++ b/arch/x86/include/asm/timex.h @@ -7,8 +7,7 @@ =20 static inline unsigned long random_get_entropy(void) { - if (!IS_ENABLED(CONFIG_X86_TSC) && - !cpu_feature_enabled(X86_FEATURE_TSC)) + if (!cpu_feature_enabled(X86_FEATURE_TSC)) return random_get_entropy_fallback(); return rdtsc(); } diff --git a/arch/x86/include/asm/trace_clock.h b/arch/x86/include/asm/trace_= clock.h index 7061a56..1efab28 100644 --- a/arch/x86/include/asm/trace_clock.h +++ b/arch/x86/include/asm/trace_clock.h @@ -5,17 +5,9 @@ #include #include =20 -#ifdef CONFIG_X86_TSC - extern u64 notrace trace_clock_x86_tsc(void); =20 # define ARCH_TRACE_CLOCKS \ { trace_clock_x86_tsc, "x86-tsc", .in_ns =3D 0 }, =20 -#else /* !CONFIG_X86_TSC */ - -#define ARCH_TRACE_CLOCKS - -#endif - #endif /* _ASM_X86_TRACE_CLOCK_H */ diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 4f7f09f..4d2d2f2 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -76,8 +76,7 @@ extern void disable_TSC(void); =20 static inline cycles_t get_cycles(void) { - if (!IS_ENABLED(CONFIG_X86_TSC) && - !cpu_feature_enabled(X86_FEATURE_TSC)) + if (!cpu_feature_enabled(X86_FEATURE_TSC)) return 0; return rdtsc(); } @@ -94,25 +93,15 @@ extern unsigned long native_calibrate_tsc(void); extern unsigned long long native_sched_clock_from_tsc(u64 tsc); =20 extern int tsc_clocksource_reliable; -#ifdef CONFIG_X86_TSC extern bool tsc_async_resets; -#else -# define tsc_async_resets false -#endif =20 /* * Boot-time check whether the TSCs are synchronized across * all CPUs/cores: */ -#ifdef CONFIG_X86_TSC extern bool tsc_store_and_check_tsc_adjust(bool bootcpu); extern void tsc_verify_tsc_adjust(bool resume); extern void check_tsc_sync_target(void); -#else -static inline bool tsc_store_and_check_tsc_adjust(bool bootcpu) { return fal= se; } -static inline void tsc_verify_tsc_adjust(bool resume) { } -static inline void check_tsc_sync_target(void) { } -#endif =20 extern int notsc_setup(char *); extern void tsc_save_sched_clock_state(void); diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 47a32f5..31f46fd 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -108,7 +108,7 @@ apm-y :=3D apm_32.o obj-$(CONFIG_APM) +=3D apm.o obj-$(CONFIG_SMP) +=3D smp.o obj-$(CONFIG_SMP) +=3D smpboot.o -obj-$(CONFIG_X86_TSC) +=3D tsc_sync.o +obj-y +=3D tsc_sync.o obj-$(CONFIG_SMP) +=3D setup_percpu.o obj-$(CONFIG_X86_MPPARSE) +=3D mpparse.o obj-y +=3D apic/ @@ -117,7 +117,7 @@ obj-$(CONFIG_DYNAMIC_FTRACE) +=3D ftrace.o obj-$(CONFIG_FUNCTION_TRACER) +=3D ftrace_$(BITS).o obj-$(CONFIG_FUNCTION_GRAPH_TRACER) +=3D ftrace.o obj-$(CONFIG_FTRACE_SYSCALLS) +=3D ftrace.o -obj-$(CONFIG_X86_TSC) +=3D trace_clock.o +obj-y +=3D trace_clock.o obj-$(CONFIG_TRACING) +=3D trace.o obj-$(CONFIG_RETHOOK) +=3D rethook.o obj-$(CONFIG_VMCORE_INFO) +=3D vmcore_info_$(BITS).o diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c index cb9852a..0b99103 100644 --- a/arch/x86/kernel/i8253.c +++ b/arch/x86/kernel/i8253.c @@ -31,7 +31,7 @@ struct clock_event_device *global_clock_event; */ static bool __init use_pit(void) { - if (!IS_ENABLED(CONFIG_X86_TSC) || !boot_cpu_has(X86_FEATURE_TSC)) + if (!boot_cpu_has(X86_FEATURE_TSC)) return true; =20 /* This also returns true when APIC is disabled */ diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index c5110eb..ce10ae4 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -298,30 +298,17 @@ notrace u64 sched_clock(void) preempt_enable_notrace(); return now; } - int check_tsc_unstable(void) { return tsc_unstable; } EXPORT_SYMBOL_GPL(check_tsc_unstable); =20 -#ifdef CONFIG_X86_TSC int __init notsc_setup(char *str) { mark_tsc_unstable("boot parameter notsc"); return 1; } -#else -/* - * disable flag for tsc. Takes effect by clearing the TSC cpu flag - * in cpu/common.c - */ -int __init notsc_setup(char *str) -{ - setup_clear_cpu_cap(X86_FEATURE_TSC); - return 1; -} -#endif __setup("notsc", notsc_setup); =20 enum {