From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FD6D36C9EC for ; Mon, 29 Jun 2026 12:00:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782734408; cv=none; b=HhXFOvXM34edTlyhmRKcnDgAjYYjqsu/vD2KlvEI6533PcvWY0VpyyKXS/WxxwlZ3XeK0cZ7nCCq7Q755dbccHlCW4ATaYCOMIsOPMisK5sPtSSWz0NvWiUWhVlau9PxBVndOfc5i8AcmiTPOg6F7pZRwT1UAuw914Q2dyXh8xw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782734408; c=relaxed/simple; bh=Os7ci8igy0UkMvrcKEoY2m0OgZNNG0gkcjcopOhHbh8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=r9gy/SkiRBGc4gLgMielflaOY0iOXes06mRQ1DIeBTO6mdqk/10ww4oHsG7JFn06dv3de5tH6KAnLKkavidWLRb96YruLml8fWDk/wbCYa2ESZvjMHQUX724slRygxBHsXKezyVoIM6S2VG9DI7xdepRkU7maXwSXDW6pHIkSoI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aCKCScNI; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aCKCScNI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2ADC91F000E9; Mon, 29 Jun 2026 12:00:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1782734407; bh=H3LMo9OUhCt7iuD9sUwObFV3HjBdU8mIDrDWMzZ4g6Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=aCKCScNIw7pY1NYDeBsU/PN8yQETYoNGnOvKW9qOn0jGqvLent2MpvdaKon7xo0Xj buSv7W1ouVicuoBqYkdTiwX01kg6xeJoym5FPcnHA0jvV+HpIDuH9+NFTIbFuKKG// 4xOY+p9Cn3xDnc4Gr7ykkqi1rqNF9adIPgF3r2qYIiYSUVye+puqD9MQhUphqiGCZT 1RdlILLnr5a4crM7xC3ucQbPAr8ac+itE2SJ6fE5X6R+JqT64OiEuzg/VN/ektNh0r xNs++EQWMkgAcABIRhhatIXkdrHQ4BiKshf5EstgaeUmEfry4vB+HFDioXqsB7NfZe A8tdAbu0pruuQ== From: Will Deacon To: linux-arm-kernel@lists.infradead.org, Anshuman Khandual Cc: catalin.marinas@arm.com, kernel-team@android.com, Will Deacon , Ryan Roberts , David Hildenbrand , linux-kernel@vger.kernel.org, Ben Hutchings Subject: Re: [PATCH] arm64/mm: Optimize TLB flush in unmap_hotplug_[pmd|pud]_range() Date: Mon, 29 Jun 2026 12:59:57 +0100 Message-ID: <178273154856.1018225.14785712662574952579.b4-ty@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260626012845.475959-1-anshuman.khandual@arm.com> References: <20260626012845.475959-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Fri, 26 Jun 2026 02:28:45 +0100, Anshuman Khandual wrote: > flush_tlb_kernel_range() could flush down an entire block mapping just with > a single PAGE_SIZE stride. This capability was being used umapping PMD and > PUD based block mappings in unmap_hotplug_[pmd|pud]_range(). > > But later on the commit 48478b9f7913 > ("arm64/mm: Enable batched TLB flush in unmap_hotplug_range()") replaced > this PAGE_SIZE stride with [PMD|PUD]_SIZE strides, hence forcing multiple > PAGE_SIZE stride based TLB flushes on platforms where TLB range operation > is not supported. Revert back to the earlier TLB behaviour along with the > required comments that were dropped earlier. > > [...] Applied to arm64 (for-next/fixes), thanks! [1/1] arm64/mm: Optimize TLB flush in unmap_hotplug_[pmd|pud]_range() https://git.kernel.org/arm64/c/ff4c5a0de1f2 Cheers, -- Will https://fixes.arm64.dev https://next.arm64.dev https://will.arm64.dev