From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ADDC3E716F; Tue, 30 Jun 2026 09:09:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782810576; cv=none; b=qs9g9p/AdjwGjRLH56p+aJ2zErRMFzHCjc1hD5qEoOZI3pNkfCIDP8H+CNSAJaGQka735Qx3Ie/SFEN0BBcjeKrM7trqmlJuySKoi8OlC9i/dZGl1Ox0gUGtGmS8W7c5LCnf7pFcR9e1Gg5LP4BzYkAUzKARosv2LrS7ijGjk4I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782810576; c=relaxed/simple; bh=NHcIsvaqM047EguKYQuCAFJCUSzSWGFFRuhiCHKcb7Q=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=SWIkiEEFVllJjH2E/DO8Xopao9VjslfGhOoZ2kJWllyVGfS0cK9QtY99zIy7b0eIqLwtrrkvLT0vrrwZxZ2WgQXo9et51rtdlKpsaCEuFYTKCnuJHkYqWSDV1VkdT44rXKgrJEgNTEit+4XNZ6dUrR6oHXrCU80LO7rgiJzFRsA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Q9OlfEBh; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=y003DT5B; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Q9OlfEBh"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="y003DT5B" Date: Tue, 30 Jun 2026 09:09:32 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1782810573; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=55+Tx6OnYz51xH8SDhL9zY01NId8pjUCvaoGXQPnHLI=; b=Q9OlfEBhBsG3en/9ek8X5gwO9UrUo7DIR4az7Amft6q6XnO7YeMMcVI3tRBjVyIvvIjdm9 02hUWC0cUu/a5QI9c7Fb+OpiBPSKyZAXTYMimxBAWs3+jZ4hvp02u9juMWf/Ghtm11lEf0 nfJtAz3TDHRj/DHLdglZtHxi+gFWZYDcuPr+CGtFAHTFk7fKVziL+stz6GXel/r7Khs/1O 8hJ+bQchTdaZ73a47KPMjp5fU+/gPV8sciEp7JWlR+LFLSSxmYMb2d5i8CHY0fPT6UzYdB L6VFhgJ74LqQZzaMesixcH973+x/sS4dUXlj++loM6Zi5ZL+lRUVetorMT3FHg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1782810573; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=55+Tx6OnYz51xH8SDhL9zY01NId8pjUCvaoGXQPnHLI=; b=y003DT5BaejBz/G72oM1YO+1L14hgwd3TQIfcB3Ri/nqk+/gtCEifSCU/cPOLvtDsLlncn J+AnKqlOZMeChFCA== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Drop fixed-counter PEBS constraints for baseline PEBS Cc: Yi Lai , Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260612090114.3188886-7-dapeng1.mi@linux.intel.com> References: <20260612090114.3188886-7-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178281057228.3843924.9335595308569147604.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 39bae9e84e203df9cc19e6f081ad806956501bb5 Gitweb: https://git.kernel.org/tip/39bae9e84e203df9cc19e6f081ad8069565= 01bb5 Author: Dapeng Mi AuthorDate: Fri, 12 Jun 2026 17:01:12 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 30 Jun 2026 10:57:06 +02:00 perf/x86/intel: Drop fixed-counter PEBS constraints for baseline PEBS On Sapphire Rapids (SPR) guests where pebs_baseline is not advertised, running command $ ./perf record -e cpu/event=3D0x00,umask=3D0x01,i\ name=3DINST_RETIRED.PREC_DIST/p -c 10000 sleep 1 can trigger: unchecked MSR access error: WRMSR to 0x3f1 ... in\ intel_pmu_pebs_enable_all() This occurs because SPR-specific PEBS constraints allow fixed-counter scheduling (for example, INST_RETIRED.PREC_DIST on fixed counter 0). In guests lacking pebs_baseline, KVM does not support PEBS sampling on fixed counters, so enabling such events reaches an invalid MSR programming path. Starting with Icelake, regardless of whether Extended PEBS or Architectural PEBS is in use, all counters (including fixed counters) support PEBS sampling, and the PMU_FL_PEBS_ALL flag is set by default. As long as PMU_FL_PEBS_ALL is set, constraint lookup automatically falls back to the corresponding non-PEBS constraints if no matching entry is found in the PEBS constraints table. Since non-PEBS event constraints already contain the same fixed-counter constraints, it is safe to remove these fixed-counter entries from the PEBS constraints table. The fallback mechanism will ensure that fixed PEBS events are scheduled onto the correct fixed counters. So, directly drop the fixed-counter entries from the PEBS constraint table. Without pebs_baseline, these fixed-counter PEBS events will now resolve to empty constraints and will not be scheduled or enabled, thereby avoiding the warning and bypassing the broken guest PEBS path. Reported-by: Yi Lai Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260612090114.3188886-7-dapeng1.mi@linux.inte= l.com --- arch/x86/events/intel/ds.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 91a093d..e86e4ba 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1444,10 +1444,6 @@ struct event_constraint intel_skl_pebs_event_constrain= ts[] =3D { }; =20 struct event_constraint intel_icl_pebs_event_constraints[] =3D { - INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL), /* old INST_RETIRED.= PREC_DIST */ - INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL), /* INST_RETIRED.PREC= _DIST */ - INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */ - INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.S= TLB_MISS_LOADS */ INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.S= TLB_MISS_STORES */ @@ -1470,9 +1466,6 @@ struct event_constraint intel_icl_pebs_event_constraint= s[] =3D { }; =20 struct event_constraint intel_glc_pebs_event_constraints[] =3D { - INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_= DIST */ - INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), - INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe), INTEL_PLD_CONSTRAINT(0x1cd, 0xfe), INTEL_PSD_CONSTRAINT(0x2cd, 0x1), @@ -1497,9 +1490,6 @@ struct event_constraint intel_glc_pebs_event_constraint= s[] =3D { }; =20 struct event_constraint intel_lnc_pebs_event_constraints[] =3D { - INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_= DIST */ - INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), - INTEL_FLAGS_UEVENT_CONSTRAINT(0x012a, 0x1), /* OCR.* events */ INTEL_FLAGS_UEVENT_CONSTRAINT(0x012b, 0x1), /* OCR.* events */ =20 @@ -1531,9 +1521,6 @@ struct event_constraint intel_lnc_pebs_event_constraint= s[] =3D { }; =20 struct event_constraint intel_pnc_pebs_event_constraints[] =3D { - INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_= DIST */ - INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), - INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0xfc), INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3), INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.S= TLB_MISS_LOADS */