From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 610CC3DC878; Tue, 30 Jun 2026 09:09:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782810578; cv=none; b=U09PN30Cq4oNvpMUrENAgqz4LiCHuI6oobJhiJJGMFAzY/1au4ZOb6Ej+3fP8TicALT0CUsc+PROOTE+or6ehFlae7OoDEdS763rIeZ4ZYmJVXl2LbwdMOyOVUmfl9HR8LdgtCW+0WIJ27FMM35+oR7uNx4kKbYno3rgGAGvjL8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782810578; c=relaxed/simple; bh=SjMcXLdBwxjHaBOsOENLfCM26JIosfjGHZcu/ILcUS0=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=byffX5wmkrtQErt7zm9ElhbvJXB571Mb7bBJ6AR29XdUE+G/3KagpSHGsMGDwe1nQF6NnXCrff2nm4ylL0vvebotXyCs56mkdGeScjAwr6eoyyxAtFMz4RNwYMqOb3LlXMbUUkHrPwtRYIi+xZ/lgWNXWM60yOI/XEqq1xykJRg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=NtswFA78; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=F2hr3t8H; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="NtswFA78"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="F2hr3t8H" Date: Tue, 30 Jun 2026 09:09:33 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1782810575; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IOra2jf+qG64q78UBnAFhpmrX9zXUePgqOev7/UvvIE=; b=NtswFA78HYENdcR2uH3TdjNHzZZDCBGeWLTIcmBgwBrLnU9hAoOP6165yldvACQ7dYzOTB S/pznOgJ8NJcb8LhwIb9U5hfGdyYOC58WXlyBQx/2fz/UzBYuMyPrQgTMWFpDoCrMJkZh1 EtLKQ9pfPuHy2/W1ajbF1yUnDvFDPSHG5eL5Dg0jBRkH7YzYpz/g3aYDNh+axMJ4ASC8v+ 0V6naQYBN9GQc40Cc2HfXDw2frkhAJZKTCixXIf8Qen//gJA2MpEgR/f2ym2jkTAJBs2Gt A8450yWvMwoKM97xT6YO7OTq6g4sMz6BvtWBNEKfTnIWoZIlVT89uRfiuolktQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1782810575; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IOra2jf+qG64q78UBnAFhpmrX9zXUePgqOev7/UvvIE=; b=F2hr3t8HTcwtmBOWC9v8sl3usGqkxvw/eZsbuN6+EKyQNigJidjNOxM8OPsBNnsg681iix VbAEx0OQNC+JRSBg== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Validate the return value of intel_pmu_init_hybrid() Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260612090114.3188886-6-dapeng1.mi@linux.intel.com> References: <20260612090114.3188886-6-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178281057360.3843924.15894857178281995778.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: cf4ffb0088287774fc4bf00b65589b4158497777 Gitweb: https://git.kernel.org/tip/cf4ffb0088287774fc4bf00b65589b41584= 97777 Author: Dapeng Mi AuthorDate: Fri, 12 Jun 2026 17:01:11 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 30 Jun 2026 10:57:06 +02:00 perf/x86/intel: Validate the return value of intel_pmu_init_hybrid() The intel_pmu_init_hybrid() function allocates memory for the x86_pmu.hybrid_pmu[] array. If this allocation fails under memory pressure, hybrid PMU initialization will fail. Currently, the caller does not check the return value of intel_pmu_init_hybrid(). This can lead to a null-pointer dereference or invalid memory access when attempting to use the uninitialized array, potentially triggering a system panic. Fix this by validating the return value of intel_pmu_init_hybrid(). Additionally, reset x86_pmu.num_hybrid_pmus to 0 on failure, and defer intel_pmu_arch_lbr_init() until after hybrid PMU initialization succeeds. This reordering avoids the need to explicitly destroy the kmem cache if the memory allocation fails. Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260612090114.3188886-6-dapeng1.mi@linux.inte= l.com --- arch/x86/events/intel/core.c | 44 +++++++++++++++++++++++------------ 1 file changed, 30 insertions(+), 14 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 5116b15..20253e7 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -7679,8 +7679,10 @@ static __always_inline int intel_pmu_init_hybrid(enum = hybrid_pmu_type pmus) x86_pmu.num_hybrid_pmus =3D hweight_long(pmus_mask); x86_pmu.hybrid_pmu =3D kzalloc_objs(struct x86_hybrid_pmu, x86_pmu.num_hybrid_pmus); - if (!x86_pmu.hybrid_pmu) + if (!x86_pmu.hybrid_pmu) { + x86_pmu.num_hybrid_pmus =3D 0; return -ENOMEM; + } =20 static_branch_enable(&perf_is_hybrid); x86_pmu.filter =3D intel_pmu_filter; @@ -7863,14 +7865,14 @@ __init int intel_pmu_init(void) struct attribute **td_attr =3D &empty_attrs; struct attribute **mem_attr =3D &empty_attrs; struct attribute **tsx_attr =3D &empty_attrs; + struct x86_hybrid_pmu *pmu; + unsigned int fixed_mask; union cpuid10_edx edx; union cpuid10_eax eax; union cpuid10_ebx ebx; - unsigned int fixed_mask; + int version, i, ret; bool pmem =3D false; - int version, i; char *name; - struct x86_hybrid_pmu *pmu; =20 /* Architectural Perfmon was introduced starting with Core "Yonah" */ if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { @@ -7940,9 +7942,6 @@ __init int intel_pmu_init(void) x86_pmu.lbr_read =3D intel_pmu_lbr_read_32; } =20 - if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) - intel_pmu_arch_lbr_init(); - intel_pebs_init(); =20 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ @@ -8540,7 +8539,9 @@ __init int intel_pmu_init(void) * * Initialize the common PerfMon capabilities here. */ - intel_pmu_init_hybrid(hybrid_big_small); + ret =3D intel_pmu_init_hybrid(hybrid_big_small); + if (ret) + return ret; =20 x86_pmu.pebs_latency_data =3D grt_latency_data; x86_pmu.get_event_constraints =3D adl_get_event_constraints; @@ -8598,7 +8599,9 @@ __init int intel_pmu_init(void) case INTEL_METEORLAKE: case INTEL_METEORLAKE_L: case INTEL_ARROWLAKE_U: - intel_pmu_init_hybrid(hybrid_big_small); + ret =3D intel_pmu_init_hybrid(hybrid_big_small); + if (ret) + return ret; =20 x86_pmu.pebs_latency_data =3D cmt_latency_data; x86_pmu.get_event_constraints =3D mtl_get_event_constraints; @@ -8629,7 +8632,9 @@ __init int intel_pmu_init(void) pr_cont("Pantherlake Hybrid events, "); name =3D "pantherlake_hybrid"; =20 - intel_pmu_init_hybrid(hybrid_big_small); + ret =3D intel_pmu_init_hybrid(hybrid_big_small); + if (ret) + return ret; =20 /* Initialize big core specific PerfMon capabilities.*/ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; @@ -8644,7 +8649,9 @@ __init int intel_pmu_init(void) pr_cont("Arrowlake Hybrid events, "); name =3D "arrowlake_hybrid"; =20 - intel_pmu_init_hybrid(hybrid_big_small); + ret =3D intel_pmu_init_hybrid(hybrid_big_small); + if (ret) + return ret; =20 /* Initialize big core specific PerfMon capabilities.*/ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; @@ -8661,7 +8668,9 @@ __init int intel_pmu_init(void) pr_cont("Lunarlake Hybrid events, "); name =3D "lunarlake_hybrid"; =20 - intel_pmu_init_hybrid(hybrid_big_small); + ret =3D intel_pmu_init_hybrid(hybrid_big_small); + if (ret) + return ret; =20 /* Initialize big core specific PerfMon capabilities.*/ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; @@ -8686,7 +8695,9 @@ __init int intel_pmu_init(void) break; =20 case INTEL_ARROWLAKE_H: - intel_pmu_init_hybrid(hybrid_big_small_tiny); + ret =3D intel_pmu_init_hybrid(hybrid_big_small_tiny); + if (ret) + return ret; =20 x86_pmu.pebs_latency_data =3D arl_h_latency_data; x86_pmu.get_event_constraints =3D arl_h_get_event_constraints; @@ -8721,7 +8732,9 @@ __init int intel_pmu_init(void) case INTEL_NOVALAKE_L: pr_cont("Novalake Hybrid events, "); name =3D "novalake_hybrid"; - intel_pmu_init_hybrid(hybrid_big_small); + ret =3D intel_pmu_init_hybrid(hybrid_big_small); + if (ret) + return ret; =20 x86_pmu.pebs_latency_data =3D nvl_latency_data; x86_pmu.get_event_constraints =3D mtl_get_event_constraints; @@ -8830,6 +8843,9 @@ __init int intel_pmu_init(void) =20 intel_pmu_check_event_constraints_all(NULL); =20 + if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) + intel_pmu_arch_lbr_init(); + /* * Access LBR MSR may cause #GP under certain circumstances. * Check all LBR MSR here.