From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 430E23E638E; Tue, 30 Jun 2026 09:09:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782810583; cv=none; b=pFa0ES2+o0/vac2oQ4NrienhT7xFbKPDhTzss31CATkYfWrMhSHqd5A75wpkl+0LGvebHWpbUw4nR7YBsTySMW9vu9v/MH/a8i+1gHiHQmvWL0mtADGkiOhQ/4TcTpXEIE1JeD9ZZ/+jR8k74CxVHDMeZfDcdHcnXoIO/gPFIzo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782810583; c=relaxed/simple; bh=tZD0efr0f7QcZCr/oDXRAJR/IUaeaw9GGWhtzOgC59U=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=ty8+sAvslv/Gbclfhrkm+gotmNhgs7O9vn5C8cNf03y8NSZvTbAVDnRzfHBNDLXaHjKPYJxVDdKGFdXyxzf1MfqUeYC0JGvT67fVmyiEW1oQ3D+POD33hrAEGJcK6KEzqHATp/QhRzKtHI6T4xRuek5cZpvCoAh+OqZ31mV1Nw0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ohSfUMYN; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=sbaOw3Nu; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ohSfUMYN"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="sbaOw3Nu" Date: Tue, 30 Jun 2026 09:09:37 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1782810578; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=D0dQhwte9zLIjxgp6I94q7eg79xTursxujS9XxsBp4A=; b=ohSfUMYNe05+jIuaKLdGT93JvFeRXvlgNRHK+7iAPsEA8//fANuICtRw3F/lqlL5ccFJ+Q Kgza7SuUY05BcYWMk3A4fSzIbPRokjViMlDchbWWxw/fVEbch6luvJa5kMb36fQbiBgCNL NIZRLZDoPxQmarBelczEWVks25fNlpWXdAL068Ell2JHaskI9+USbmpYwIc0Ztk4G1uDkM vpfbnudQhLi8FNkWBeYrcNZYID8B5E73DG8+uJw+lMjT3FKjE08pPT7S71zNRUZYifP5e6 etgWRk1xF8lhhJaU2+HNPnBgagS7cEA1Foe4XDAIXh2ejJkZtEtz27v0W5HMDQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1782810578; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=D0dQhwte9zLIjxgp6I94q7eg79xTursxujS9XxsBp4A=; b=sbaOw3NugmvfUUvMCndeZqpVRFs54euFNMVo8SdXu37UyYtmOo09e2UCm4LcG2Z02If/cL yosr8Z/zhu1waDDg== From: "tip-bot2 for Dapeng Mi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Keep cap_user_rdpmc in sync with RDPMC user-disable state Cc: Dapeng Mi , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260612090114.3188886-3-dapeng1.mi@linux.intel.com> References: <20260612090114.3188886-3-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178281057723.3843924.7693467293605091884.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the perf/core branch of tip: Commit-ID: 503c7184ca6a5e1f5b53466621d94fa413f3bad9 Gitweb: https://git.kernel.org/tip/503c7184ca6a5e1f5b53466621d94fa413f= 3bad9 Author: Dapeng Mi AuthorDate: Fri, 12 Jun 2026 17:01:08 +08:00 Committer: Peter Zijlstra CommitterDate: Tue, 30 Jun 2026 10:57:05 +02:00 perf/x86/intel: Keep cap_user_rdpmc in sync with RDPMC user-disable state After introducing the RDPMC user disable feature, user-space RDPMC may return 0 instead of the actual event count. This creates an inconsistency with cap_user_rdpmc, where cap_user_rdpmc is set, but user-space RDPMC only returns 0. To accurately represent the user-space RDPMC capability, update cap_user_rdpmc (depending on PERF_EVENT_FLAG_USER_READ_CNT) according to the RDPMC user disable state. If RDPMC user disable is enabled, cap_user_rdpmc is updated to false eventually, allowing user-space programs to fall back to the read() syscall to obtain the real event count. Because PERF_EVENT_FLAG_USER_READ_CNT is evaluated in x86_pmu_event_init(), move intel_pmu_update_rdpmc_user_disable() earlier into intel_pmu_hw_config(). This ensures that the user-disable state is updated before updating PERF_EVENT_FLAG_USER_READ_CNT. Note that since event->ctx is not yet assigned at this stage, use the PERF_ATTACH_TASK flag to detect whether the event is task-attached. While at it, fix the indentation of x86_pmu_has_rdpmc_user_disable() to adhere to the kernel coding style. Fixes: 59af95e028d4 ("perf/x86/intel: Add support for rdpmc user disable feat= ure") Signed-off-by: Dapeng Mi Signed-off-by: Peter Zijlstra (Intel) Link: https://patch.msgid.link/20260612090114.3188886-3-dapeng1.mi@linux.inte= l.com --- arch/x86/events/core.c | 3 ++- arch/x86/events/intel/core.c | 6 +++--- arch/x86/events/perf_event.h | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index d1af33d..af0b67f 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2539,7 +2539,8 @@ static int x86_pmu_event_init(struct perf_event *event) } =20 if (READ_ONCE(x86_pmu.attr_rdpmc) && - !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) + !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS) && + !(event->hw.config & ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE)) event->hw.flags |=3D PERF_EVENT_FLAG_USER_READ_CNT; =20 return err; diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 465c414..5116b15 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3533,7 +3533,7 @@ static void intel_pmu_update_rdpmc_user_disable(struct = perf_event *event) */ if (x86_pmu.attr_rdpmc =3D=3D X86_USER_RDPMC_ALWAYS_ENABLE || (x86_pmu.attr_rdpmc =3D=3D X86_USER_RDPMC_CONDITIONAL_ENABLE && - event->ctx->task)) + (event->attach_state & PERF_ATTACH_TASK))) event->hw.config &=3D ~ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE; else event->hw.config |=3D ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE; @@ -3547,8 +3547,6 @@ static void intel_pmu_enable_event(struct perf_event *e= vent) struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; =20 - intel_pmu_update_rdpmc_user_disable(event); - if (unlikely(event->attr.precise_ip)) static_call(x86_pmu_pebs_enable)(event); =20 @@ -5147,6 +5145,8 @@ static int intel_pmu_hw_config(struct perf_event *event) leader->hw.flags |=3D PERF_X86_EVENT_ACR; } =20 + intel_pmu_update_rdpmc_user_disable(event); + if ((event->attr.type =3D=3D PERF_TYPE_HARDWARE) || (event->attr.type =3D=3D PERF_TYPE_HW_CACHE)) return 0; diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 5902a29..a8afea8 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1344,7 +1344,7 @@ static inline u64 x86_pmu_get_event_config(struct perf_= event *event) static inline bool x86_pmu_has_rdpmc_user_disable(struct pmu *pmu) { return !!(hybrid(pmu, config_mask) & - ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE); + ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE); } =20 extern struct event_constraint emptyconstraint;