From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B47C3377006; Thu, 2 Jul 2026 10:15:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782987359; cv=none; b=dlnPL6rk9K4kk1FTJtPQCrRxbavlzhHEG8xaNu59cILQPYd1SIPDtzXQLuA+lxvoVla12ZEw4Wiz6A/i3FC0Ok84PnU+5a3jt2ZkIhgB2mghj3WNutbRThk4j9sCWBqrCIKf5xzWwE2vnGLrRw8IyvUpZuniLxbZJRQTIhE0GOE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782987359; c=relaxed/simple; bh=xjHTeimFSOAmTkrhmbuuVlU2G1OX0X+juvZFxVMLpX4=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=k2Neyr8AMNvgq+BV/oiTSTfsYht/LPGrUBj5QSy5twY1ICpCKIhBILzonubtfkF5RsAc9vud2zpZQfnOdajdnTB0jqIL8Ufiyr3xACx+DZD1eNqy2DFMtI76TJM93ANIz47x4TT+B0oKixslWpw0gtqSY1L7T59R+cEDtXj+wMk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=U0u3Q6ZS; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=IXa9W/MG; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="U0u3Q6ZS"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="IXa9W/MG" Date: Thu, 02 Jul 2026 10:15:54 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1782987356; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DpZstuJfeUP31/fIzC7S6A4gC2quO3h8k0+b0MG0duA=; b=U0u3Q6ZSk5DKqpxvls/EirS/BsZwI4vmF6RlDLXe4N5TUR179n5BY+Kopu0mVog0b539Nr VzgWmw9pHQ5qZCp8EI50akxE3SOm5LhexXwzm5vt9R4RtVUno+z9faZcRIOz5oKKb0DIex hftMfEXa7vY8oLQO6gP111ZSwf8Nzaa5/a9pY07jEu2SDRzdM8zOqZrnFSeO9thPT8wsgq lECUWaNH2FI0pfj4RxlK1W96Ndw4H+Tk8zsJhk/L2UWuT0LXKmWHbliO55zldS/ENr80EI dlXYZrNsl4lH7g34f8dwRGkUDxbLcY7gLA8siD8mm0fAxIexHbDabGATpL0x1Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1782987356; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DpZstuJfeUP31/fIzC7S6A4gC2quO3h8k0+b0MG0duA=; b=IXa9W/MGU/tGS8ywOC2wZ128vmAzV2B16iFUGGo+v80zvhDlC5z7/fq8Z0ALZ7vXJaMbY1 TpkBW03YzzpIq7Bw== From: "tip-bot2 for Juergen Gross" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/msr] x86/cpu: Stop using 32-bit MSR interfaces Cc: Juergen Gross , Ingo Molnar , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260629060526.3638272-20-jgross@suse.com> References: <20260629060526.3638272-20-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178298735495.3843924.289690164073708304.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/msr branch of tip: Commit-ID: 2e9e6edbad45fe9078dfb2d35d1213c9969de49d Gitweb: https://git.kernel.org/tip/2e9e6edbad45fe9078dfb2d35d1213c9969= de49d Author: Juergen Gross AuthorDate: Mon, 29 Jun 2026 08:05:10 +02:00 Committer: Ingo Molnar CommitterDate: Thu, 02 Jul 2026 11:54:52 +02:00 x86/cpu: Stop using 32-bit MSR interfaces The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be removed. Use the related 64-bit variants instead. Signed-off-by: Juergen Gross Signed-off-by: Ingo Molnar Link: https://patch.msgid.link/20260629060526.3638272-20-jgross@suse.com --- arch/x86/kernel/cpu/centaur.c | 35 ++++++++++++++++---------------- arch/x86/kernel/cpu/common.c | 12 ++++++----- arch/x86/kernel/cpu/intel.c | 8 +++---- arch/x86/kernel/cpu/transmeta.c | 9 ++++---- arch/x86/kernel/cpu/zhaoxin.c | 12 ++++------- 5 files changed, 39 insertions(+), 37 deletions(-) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 681d2da..513fa1f 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -22,7 +22,7 @@ =20 static void init_c3(struct cpuinfo_x86 *c) { - u32 lo, hi; + u64 msr; =20 /* Test for Centaur Extended Feature Flags presence */ if (cpuid_eax(0xC0000000) >=3D 0xC0000001) { @@ -30,17 +30,17 @@ static void init_c3(struct cpuinfo_x86 *c) =20 /* enable ACE unit, if present and disabled */ if ((tmp & (ACE_PRESENT | ACE_ENABLED)) =3D=3D ACE_PRESENT) { - rdmsr(MSR_VIA_FCR, lo, hi); - lo |=3D ACE_FCR; /* enable ACE unit */ - wrmsr(MSR_VIA_FCR, lo, hi); + rdmsrq(MSR_VIA_FCR, msr); + /* enable ACE unit */ + wrmsrq(MSR_VIA_FCR, msr | ACE_FCR); pr_info("CPU: Enabled ACE h/w crypto\n"); } =20 /* enable RNG unit, if present and disabled */ if ((tmp & (RNG_PRESENT | RNG_ENABLED)) =3D=3D RNG_PRESENT) { - rdmsr(MSR_VIA_RNG, lo, hi); - lo |=3D RNG_ENABLE; /* enable RNG unit */ - wrmsr(MSR_VIA_RNG, lo, hi); + rdmsrq(MSR_VIA_RNG, msr); + /* enable RNG unit */ + wrmsrq(MSR_VIA_RNG, msr | RNG_ENABLE); pr_info("CPU: Enabled h/w RNG\n"); } =20 @@ -52,9 +52,8 @@ static void init_c3(struct cpuinfo_x86 *c) #ifdef CONFIG_X86_32 /* Cyrix III family needs CX8 & PGE explicitly enabled. */ if (c->x86_model >=3D 6 && c->x86_model <=3D 13) { - rdmsr(MSR_VIA_FCR, lo, hi); - lo |=3D (1<<1 | 1<<7); - wrmsr(MSR_VIA_FCR, lo, hi); + rdmsrq(MSR_VIA_FCR, msr); + wrmsrq(MSR_VIA_FCR, msr | (1 << 1 | 1 << 7)); set_cpu_cap(c, X86_FEATURE_CX8); } =20 @@ -115,8 +114,9 @@ static void init_centaur(struct cpuinfo_x86 *c) char *name; u32 fcr_set =3D 0; u32 fcr_clr =3D 0; - u32 lo, hi, newlo; + u32 newlo; u32 aa, bb, cc, dd; + struct msr val; #endif early_init_centaur(c); init_intel_cacheinfo(c); @@ -169,15 +169,16 @@ static void init_centaur(struct cpuinfo_x86 *c) name =3D "??"; } =20 - rdmsr(MSR_IDT_FCR1, lo, hi); - newlo =3D (lo|fcr_set) & (~fcr_clr); + rdmsrq(MSR_IDT_FCR1, val.q); + newlo =3D (val.l | fcr_set) & (~fcr_clr); =20 - if (newlo !=3D lo) { + if (newlo !=3D val.l) { pr_info("Centaur FCR was 0x%X now 0x%X\n", - lo, newlo); - wrmsr(MSR_IDT_FCR1, newlo, hi); + val.l, newlo); + val.l =3D newlo; + wrmsrq(MSR_IDT_FCR1, val.q); } else { - pr_info("Centaur FCR is 0x%X\n", lo); + pr_info("Centaur FCR is 0x%X\n", val.l); } /* Emulate MTRRs using Centaur's MCR. */ set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index a3df21d..cbef2c6 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -339,16 +339,16 @@ bool cpuid_feature(void) =20 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) { - unsigned long lo, hi; + struct msr val; =20 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) return; =20 /* Disable processor serial number: */ =20 - rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); - lo |=3D 0x200000; - wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); + rdmsrq(MSR_IA32_BBL_CR_CTL, val.q); + val.l |=3D 0x200000; + wrmsrq(MSR_IA32_BBL_CR_CTL, val.q); =20 pr_notice("CPU serial number disabled.\n"); clear_cpu_cap(c, X86_FEATURE_PN); @@ -2299,8 +2299,10 @@ static inline void idt_syscall_init(void) /* May not be marked __init: used by software suspend */ void syscall_init(void) { + struct msr val =3D { .h =3D (__USER32_CS << 16) | __KERNEL_CS }; + /* The default user and kernel segments */ - wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); + wrmsrq(MSR_STAR, val.q); =20 /* * Except the IA32_STAR MSR, there is NO need to setup SYSCALL and diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index abb3984..076bdd0 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -542,12 +542,12 @@ static void init_intel(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); =20 if (boot_cpu_has(X86_FEATURE_DS)) { - unsigned int l1, l2; + u64 l; =20 - rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); - if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)) + rdmsrq(MSR_IA32_MISC_ENABLE, l); + if (!(l & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)) set_cpu_cap(c, X86_FEATURE_BTS); - if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) + if (!(l & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) set_cpu_cap(c, X86_FEATURE_PEBS); } =20 diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmeta.c index 1fdcd69..c670fbb 100644 --- a/arch/x86/kernel/cpu/transmeta.c +++ b/arch/x86/kernel/cpu/transmeta.c @@ -24,7 +24,8 @@ static void early_init_transmeta(struct cpuinfo_x86 *c) =20 static void init_transmeta(struct cpuinfo_x86 *c) { - unsigned int cap_mask, uk, max, dummy; + u64 msr; + unsigned int max, dummy; unsigned int cms_rev1, cms_rev2; unsigned int cpu_rev, cpu_freq =3D 0, cpu_flags, new_cpu_rev; char cpu_info[65]; @@ -86,10 +87,10 @@ static void init_transmeta(struct cpuinfo_x86 *c) } =20 /* Unhide possibly hidden capability flags */ - rdmsr(0x80860004, cap_mask, uk); - wrmsr(0x80860004, ~0, uk); + rdmsrq(0x80860004, msr); + wrmsrq(0x80860004, msr | ~0U); c->x86_capability[CPUID_1_EDX] =3D cpuid_edx(0x00000001); - wrmsr(0x80860004, cap_mask, uk); + wrmsrq(0x80860004, msr); =20 /* All Transmeta CPUs have a constant TSC */ set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index 761aef5..fe504fd 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -21,7 +21,7 @@ =20 static void init_zhaoxin_cap(struct cpuinfo_x86 *c) { - u32 lo, hi; + u64 msr; =20 /* Test for Extended Feature Flags presence */ if (cpuid_eax(0xC0000000) >=3D 0xC0000001) { @@ -29,19 +29,17 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c) =20 /* Enable ACE unit, if present and disabled */ if ((tmp & (ACE_PRESENT | ACE_ENABLED)) =3D=3D ACE_PRESENT) { - rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); + rdmsrq(MSR_ZHAOXIN_FCR57, msr); /* Enable ACE unit */ - lo |=3D ACE_FCR; - wrmsr(MSR_ZHAOXIN_FCR57, lo, hi); + wrmsrq(MSR_ZHAOXIN_FCR57, msr | ACE_FCR); pr_info("CPU: Enabled ACE h/w crypto\n"); } =20 /* Enable RNG unit, if present and disabled */ if ((tmp & (RNG_PRESENT | RNG_ENABLED)) =3D=3D RNG_PRESENT) { - rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); + rdmsrq(MSR_ZHAOXIN_FCR57, msr); /* Enable RNG unit */ - lo |=3D RNG_ENABLE; - wrmsr(MSR_ZHAOXIN_FCR57, lo, hi); + wrmsrq(MSR_ZHAOXIN_FCR57, msr | RNG_ENABLE); pr_info("CPU: Enabled h/w RNG\n"); } =20