From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CB4C46AF20; Thu, 2 Jul 2026 10:16:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782987362; cv=none; b=dhHqzidT7GvhlMDTQxh2GtZgfP4vRbXQt+PEDUzIbBwhN8Wspy1HhtdBuocfnFLdX/6pm+V5Hvk8nZUuajbX9U/ITgBDSqGRN5Q8iErhMQuBuBDf370XUvAOVUcmMK9x1jVnA1AYwO+JafyyjNeHkxDdtgYGVHB//RiN6oMsP4g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782987362; c=relaxed/simple; bh=1Hq+8H+sMHBp8p2oRZDevzw/lfSkxIUGlqB9D/tY82I=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=KJ5uNLmjED0jNId5BIOFCIzEtJVCSVEUvEvvtqhIfOzxoYo/wFO6a/jTQXRl2MUvWxczMphNwNfCWX27bd5+OzLGxh0jaiT41zMQbB380nlafl6GRIBCgvwlbngyO9TUkfCeC8Jk54p0Ki+VPYvZo9MHqo5PL6tStxKuHhKGDYc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=TneRsLaL; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=N4/EAHqI; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="TneRsLaL"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="N4/EAHqI" Date: Thu, 02 Jul 2026 10:15:57 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1782987359; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AyodfI2m5GvNLk7/JSl5BZ6xgF/qd0b9E3HaIL5TIlM=; b=TneRsLaLVcHwjrGRCXVVx7Cj1zbAvteKse7YMMHJzkgyIrn+AjEwt3yDZqI4fadBjKALVI +usRH+z31VmXHSbGdTuVizA+jeE1G8i1E6axtLzol4b819cGHoWm9ze+CPVdiYxFDsFBR6 hwWNzrNtJ8IwTj/u4vAudi2rv4YmuATvo+Z890SozQLQ71x/a6mIAO4j76zH2p4scjY34g PZ4lDs3znDvgVUOgBb2JfwkFr6eU20y4phqns2Ql2L7VSH8kUz/3jiLf+MZmgSTP5GcQtC 69O8Rm6p8PloaSF5FNKtBTl0iGV01ub3eiYwqSk9yNMhYN8jNOHP5BQMvVbn9Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1782987359; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AyodfI2m5GvNLk7/JSl5BZ6xgF/qd0b9E3HaIL5TIlM=; b=N4/EAHqIVDpInsy/ujpRnE4N7nSrvXLdwbCcu5IGeKNcISsRzJO5wV+Zsr6Jcci8oIeTQz IGtqj2AU0JEGPBBQ== From: "tip-bot2 for Juergen Gross" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/msr] x86/resctrl: Stop using 32-bit MSR interfaces Cc: Juergen Gross , Ingo Molnar , Reinette Chatre , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260629060526.3638272-18-jgross@suse.com> References: <20260629060526.3638272-18-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178298735765.3843924.3030867099745672963.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/msr branch of tip: Commit-ID: 4967c466ca3860fcc3ae70fee286f220020774fe Gitweb: https://git.kernel.org/tip/4967c466ca3860fcc3ae70fee286f220020= 774fe Author: Juergen Gross AuthorDate: Mon, 29 Jun 2026 08:05:08 +02:00 Committer: Ingo Molnar CommitterDate: Thu, 02 Jul 2026 11:54:52 +02:00 x86/resctrl: Stop using 32-bit MSR interfaces The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be removed. Use the related 64-bit variants instead. Signed-off-by: Juergen Gross Signed-off-by: Ingo Molnar Acked-by: Reinette Chatre Link: https://patch.msgid.link/20260629060526.3638272-18-jgross@suse.com --- arch/x86/include/asm/resctrl.h | 5 +++- arch/x86/kernel/cpu/resctrl/core.c | 7 ++++-- arch/x86/kernel/cpu/resctrl/monitor.c | 27 ++++++++++++---------- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 12 +++++----- 4 files changed, 30 insertions(+), 21 deletions(-) diff --git a/arch/x86/include/asm/resctrl.h b/arch/x86/include/asm/resctrl.h index 575f840..8f6edcd 100644 --- a/arch/x86/include/asm/resctrl.h +++ b/arch/x86/include/asm/resctrl.h @@ -102,6 +102,7 @@ static inline void __resctrl_sched_in(struct task_struct = *tsk) struct resctrl_pqr_state *state =3D this_cpu_ptr(&pqr_state); u32 closid =3D READ_ONCE(state->default_closid); u32 rmid =3D READ_ONCE(state->default_rmid); + struct msr val; u32 tmp; =20 /* @@ -123,7 +124,9 @@ static inline void __resctrl_sched_in(struct task_struct = *tsk) if (closid !=3D state->cur_closid || rmid !=3D state->cur_rmid) { state->cur_closid =3D closid; state->cur_rmid =3D rmid; - wrmsr(MSR_IA32_PQR_ASSOC, rmid, closid); + val.l =3D rmid; + val.h =3D closid; + wrmsrq(MSR_IA32_PQR_ASSOC, val.q); } } =20 diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl= /core.c index 9c01d25..f452e8c 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -725,13 +725,16 @@ static void domain_remove_cpu(int cpu, struct rdt_resou= rce *r) static void clear_closid_rmid(int cpu) { struct resctrl_pqr_state *state =3D this_cpu_ptr(&pqr_state); + struct msr val =3D { + .l =3D RESCTRL_RESERVED_RMID, + .h =3D RESCTRL_RESERVED_CLOSID + }; =20 state->default_closid =3D RESCTRL_RESERVED_CLOSID; state->default_rmid =3D RESCTRL_RESERVED_RMID; state->cur_closid =3D RESCTRL_RESERVED_CLOSID; state->cur_rmid =3D RESCTRL_RESERVED_RMID; - wrmsr(MSR_IA32_PQR_ASSOC, RESCTRL_RESERVED_RMID, - RESCTRL_RESERVED_CLOSID); + wrmsrq(MSR_IA32_PQR_ASSOC, val.q); } =20 static int resctrl_arch_online_cpu(unsigned int cpu) diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resc= trl/monitor.c index 03ee610..153dc5a 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -136,7 +136,7 @@ static int logical_rmid_to_physical_rmid(int cpu, int lrm= id) =20 static int __rmid_read_phys(u32 prmid, enum resctrl_event_id eventid, u64 *v= al) { - u64 msr_val; + struct msr msr_val =3D { .l =3D eventid, .h =3D prmid }; =20 /* * As per the SDM, when IA32_QM_EVTSEL.EvtID (bits 7:0) is configured @@ -146,15 +146,15 @@ static int __rmid_read_phys(u32 prmid, enum resctrl_eve= nt_id eventid, u64 *val) * IA32_QM_CTR.Error (bit 63) and IA32_QM_CTR.Unavailable (bit 62) * are error bits. */ - wrmsr(MSR_IA32_QM_EVTSEL, eventid, prmid); - rdmsrq(MSR_IA32_QM_CTR, msr_val); + wrmsrq(MSR_IA32_QM_EVTSEL, msr_val.q); + rdmsrq(MSR_IA32_QM_CTR, msr_val.q); =20 - if (msr_val & RMID_VAL_ERROR) + if (msr_val.q & RMID_VAL_ERROR) return -EIO; - if (msr_val & RMID_VAL_UNAVAIL) + if (msr_val.q & RMID_VAL_UNAVAIL) return -EINVAL; =20 - *val =3D msr_val; + *val =3D msr_val.q; return 0; } =20 @@ -278,7 +278,10 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, struc= t rdt_domain_hdr *hdr, =20 static int __cntr_id_read(u32 cntr_id, u64 *val) { - u64 msr_val; + struct msr msr_val =3D { + .l =3D ABMC_EXTENDED_EVT_ID | ABMC_EVT_ID, + .h =3D cntr_id + }; =20 /* * QM_EVTSEL Register definition: @@ -301,15 +304,15 @@ static int __cntr_id_read(u32 cntr_id, u64 *val) * ID is set in the QM_EVTSEL.RMID field. The RMID_VAL_UNAVAIL bit * is set if the counter data is unavailable. */ - wrmsr(MSR_IA32_QM_EVTSEL, ABMC_EXTENDED_EVT_ID | ABMC_EVT_ID, cntr_id); - rdmsrq(MSR_IA32_QM_CTR, msr_val); + wrmsrq(MSR_IA32_QM_EVTSEL, msr_val.q); + rdmsrq(MSR_IA32_QM_CTR, msr_val.q); =20 - if (msr_val & RMID_VAL_ERROR) + if (msr_val.q & RMID_VAL_ERROR) return -EIO; - if (msr_val & RMID_VAL_UNAVAIL) + if (msr_val.q & RMID_VAL_UNAVAIL) return -EINVAL; =20 - *val =3D msr_val; + *val =3D msr_val.q; return 0; } =20 diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/= resctrl/pseudo_lock.c index de580ec..d7caab0 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -241,16 +241,16 @@ int resctrl_arch_pseudo_lock_fn(void *_plr) int resctrl_arch_measure_cycles_lat_fn(void *_plr) { struct pseudo_lock_region *plr =3D _plr; - u32 saved_low, saved_high; unsigned long i; u64 start, end; void *mem_r; + u64 saved; =20 local_irq_disable(); /* * Disable hardware prefetchers. */ - rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); + rdmsrq(MSR_MISC_FEATURE_CONTROL, saved); wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); mem_r =3D READ_ONCE(plr->kmem); /* @@ -267,7 +267,7 @@ int resctrl_arch_measure_cycles_lat_fn(void *_plr) end =3D rdtsc_ordered(); trace_pseudo_lock_mem_latency((u32)(end - start)); } - wrmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); + wrmsrq(MSR_MISC_FEATURE_CONTROL, saved); local_irq_enable(); plr->thread_done =3D 1; wake_up_interruptible(&plr->lock_thread_wq); @@ -312,11 +312,11 @@ static int measure_residency_fn(struct perf_event_attr = *miss_attr, u64 hits_before =3D 0, hits_after =3D 0, miss_before =3D 0, miss_after =3D = 0; struct perf_event *miss_event, *hit_event; int hit_pmcnum, miss_pmcnum; - u32 saved_low, saved_high; unsigned int line_size; unsigned int size; unsigned long i; void *mem_r; + u64 saved; u64 tmp; =20 miss_event =3D perf_event_create_kernel_counter(miss_attr, plr->cpu, @@ -346,7 +346,7 @@ static int measure_residency_fn(struct perf_event_attr *m= iss_attr, /* * Disable hardware prefetchers. */ - rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); + rdmsrq(MSR_MISC_FEATURE_CONTROL, saved); wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); =20 /* Initialize rest of local variables */ @@ -405,7 +405,7 @@ static int measure_residency_fn(struct perf_event_attr *m= iss_attr, */ rmb(); /* Re-enable hardware prefetchers */ - wrmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); + wrmsrq(MSR_MISC_FEATURE_CONTROL, saved); local_irq_enable(); out_hit: perf_event_release_kernel(hit_event);