From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4D82352005; Tue, 7 Jul 2026 03:21:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783394515; cv=none; b=VrSYTJ7k1eWtO4B5FJ+/gOIPdkvBm0BSAwxjDBUGP2nzNuZNE97weDn2C7yQVv48SgL6DqNiaELj9xCm643u/I4mVsaaN56AlZ5jPt6eQxJf2F1DsQkZTnM9O/WeFzWXKZ+oxMZ5kwqg+exRGhkPLV1K90MoffR82Ejck0rtbFk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783394515; c=relaxed/simple; bh=i0zTWYp4eomofffZxLfQys8DIT3WICFBOm2KljJFKC8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HtdffNILHGL3gfWOV+W5YfSTfKl6B49KC0WoHZmaedzfa8lCUcIFLFQ+qxa+PpKnONUso6i4Qyd4dQGY8jVOkJMbcqZmH5juUp0nXMTGmtMZ9RztLEFbcLOKPVP45E9n4ZhkW3rZt69d4Ze5WwjO9blokSPSzLkhaFgrXp7778k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PxbPt4rw; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PxbPt4rw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4E7661F00A3E; Tue, 7 Jul 2026 03:21:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783394511; bh=7JCcMo7dAqtxx7WarVnyQrs/nKqtwRpOuvjPyWW92Qw=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=PxbPt4rwo1jbIIbBtD8uJ9eVcDVxpi+Ctk8NdtkvakJK3kHKSJHoKHCM+Ddeucndh /u4T4dqWzIa5sw53EnWs9DhPniI6SEr6CCKM1PW1P+5kkNkPk5efFgK9yay2cbp72l aK9DBwjFNhKskRo4Ov2jMH6Lu0NBmg38IYequ3S7P4Nx/e/ilCdNDnipct9CyVy+Cr 4Ra3DxwLWs3KFsyLqRiFAHt5Z8Dzkt9f+4g+gE1rUxm1d36i9XGbBEDscKLfqIIjoA 1+PkP2bwn8PCjVBp3exw2bJJgwcRIpRGuGimA/0WbSHbAeE45SNOUI8AfIdrelVwYZ l+cfxZeaeR4/Q== From: Bjorn Andersson To: Michael Turquette , Stephen Boyd , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Luo Jie Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_pavir@quicinc.com, quic_suruchia@quicinc.com, Krzysztof Kozlowski Subject: Re: (subset) [PATCH v2 0/5] Add CMN PLL clock controller support for IPQ5332 Date: Mon, 6 Jul 2026 22:21:26 -0500 Message-ID: <178339449900.1938770.10101763662447473602.b4-ty@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260106-qcom_ipq5332_cmnpll-v2-0-f9f7e4efbd79@oss.qualcomm.com> References: <20260106-qcom_ipq5332_cmnpll-v2-0-f9f7e4efbd79@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Tue, 06 Jan 2026 21:35:09 -0800, Luo Jie wrote: > This patch series adds support for the CMN PLL block on the IPQ5332 SoC. > The CMN PLL implementation in IPQ5332 is largely similar to that of > IPQ9574, which is already supported by the driver. The primary difference > is that the fixed output clocks to PPE from the CMN PLL operate at 200 MHz. > > Additionally, IPQ5332 provides a single 50 MHz clock to both UNIPHY (PCS) > instances, which in turn supply either 25 MHz or 50 MHz to the connected > Ethernet PHY or switch. > > [...] Applied, thanks! [4/5] arm64: dts: ipq5332: Add CMN PLL node for networking hardware commit: eba1bea1123924f8bf187ad175d1667036f34e80 [5/5] arm64: dts: qcom: Represent xo_board as fixed-factor clock on IPQ5332 commit: 985650336dcfe8fa640196a49956c5983dfe2696 Best regards, -- Bjorn Andersson