From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA85D3BE148; Tue, 7 Jul 2026 20:33:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783456385; cv=none; b=aLx0Ym3JCynaHpcJlHZXrtsynJe8lCauAWq0awYO5BOUy5D/gdwrMV/M9sAK7s8EeGbhHiBHeWCHO9V+EDOxhqG9syvThz57d1jXC57IveGmh1qaQLw5auSK8XhxMFR477oTCjp7RVrd2gVjM15lALZC5u3iOn7OnwPyZ/M1LVQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783456385; c=relaxed/simple; bh=Y2m3lRt6AtsxCycryJkqx04hrQ4qOJ1+OUu7OgXCoXg=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=dLcIakhH/Brul58wWuYA/TbLk0XKfOvvy3Hb6GXURtyFc2bOw4k/83y818GetrBwmdlhN2gW30S424EHacvxuQ2U5loWIf9aM/bQ3XcB/2oQjq4dgi/8bmLoBXNyGhLXjyQjPWIjwnM+gTDO9lNz3BZiDWpxcYNESaVccBkOt+U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=z2Lx77F5; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=QUDXhwi6; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="z2Lx77F5"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="QUDXhwi6" Date: Tue, 07 Jul 2026 20:33:00 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1783456382; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Yx3kOITzRuGVSauIuuJNhhomVo935SNcK5u6cvv16Io=; b=z2Lx77F5VLaOlGcxTd2yCRg3v6RL7+ufleMtBZCd+8TmLILl5ltHBxA1qYJzhrier5h5Lb bRAUdR1wvtf0tgIpkhX4xu2Cj9T8MMYnhWvXk6zlQEwKOWKHCHxUawgOTQ73u0JtRXqa+s KhYosfj6H7OJb+GinUP47RcFAK+QzNBpnK/qroxbSCm9Bh6Fz5P86yxvNjur1GQ5zCSklg j5fgeSJLd75TnOdwPzYzDTEZQSVU9Cx09US48uHmxV2zOj6VBAPngazQamiy4xF2vFP0sg zF1q4D8s+1/05F7HNkTm1kW1nmvMsO5xiMAaN/UqM6DdkHXeKR+e7FxFDEydWA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1783456382; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Yx3kOITzRuGVSauIuuJNhhomVo935SNcK5u6cvv16Io=; b=QUDXhwi6iBKWvO9NaB1wGc5EvSc+W8TPa0La1iZ5mhpJDKnELNsNt1cXOzKeWTHH+lKutx kTV/5rt1ApMNVWCA== From: "tip-bot2 for Maulik Shah" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/drivers] irqchip/qcom-pdc: Move all static variables to struct pdc_desc Cc: Maulik Shah , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260707-hamoa_pdc_v3-v4-2-dfd1f4a3ae89@oss.qualcomm.com> References: <20260707-hamoa_pdc_v3-v4-2-dfd1f4a3ae89@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178345638075.744054.1291173133577292971.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/drivers branch of tip: Commit-ID: 60caa95aa14aed8d05abc03b70e2ff14e5ab6820 Gitweb: https://git.kernel.org/tip/60caa95aa14aed8d05abc03b70e2ff14e5a= b6820 Author: Maulik Shah AuthorDate: Tue, 07 Jul 2026 14:51:34 +05:30 Committer: Thomas Gleixner CommitterDate: Tue, 07 Jul 2026 22:03:09 +02:00 irqchip/qcom-pdc: Move all static variables to struct pdc_desc There are multiple static variables used in the driver. Move all to struct pdc_desc to better align with versioning support. Document them. Add a new pdc->enable_intr() callback to point to the respective versions specific enable function. Remove pdc_enable_intr() and __pdc_enable_intr() and invoke pdc->enable_intr() from the call sites. Locking in pdc_enable_intr() applies lock to all version specific pdc->enable_intr() however lock is needed only for pdc_enable_intr_bank() which uses a shared bank across on PDC v2.7 and PDC v3.0. pdc_enable_intr_cfg() do not require locking as IRQ_CFG registers are one per interrupt. Move the locking to pdc_enable_intr_bank(). No functional impact intended [ tglx: Massage change log. ] Signed-off-by: Maulik Shah Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260707-hamoa_pdc_v3-v4-2-dfd1f4a3ae89@oss.qu= alcomm.com --- drivers/irqchip/qcom-pdc.c | 84 ++++++++++++++++++------------------- 1 file changed, 41 insertions(+), 43 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 3d272a8..5100a10 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -92,15 +92,30 @@ struct pdc_irq_cfg { * @base: PDC base register for DRV2 / HLOS * @prev_base: PDC DRV1 base, applicable only for x1e RTL bug. * @version: PDC version + * @region: PDC interrupt continuous range + * @region_cnt: Total PDC ranges + * @x1e_quirk: x1e H/W Bug handling + * @lock: lock for IRQ_ENABLE_BANK protection * @regs: PDC regs (IRQ_ENABLE_BANK and IRQ_CFG) * @cfg_fields: Fields of IRQ_CFG reg + * @enable_intr: pointer to enable function based on PDC version */ struct pdc_desc { void __iomem *base; void __iomem *prev_base; u32 version; + + struct pdc_pin_region *region; + int region_cnt; + + bool x1e_quirk; + + raw_spinlock_t lock; + const struct pdc_regs *regs; const struct pdc_irq_cfg *cfg_fields; + + void (*enable_intr)(int pin_out, bool on); }; =20 static const struct pdc_regs pdc_v3_2 =3D { @@ -138,11 +153,6 @@ struct pdc_pin_region { =20 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) =20 -static DEFINE_RAW_SPINLOCK(pdc_lock); -static struct pdc_pin_region *pdc_region; -static int pdc_region_cnt; -static unsigned int pdc_version; -static bool pdc_x1e_quirk; static struct pdc_desc *pdc; =20 static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val) @@ -196,10 +206,12 @@ static void pdc_enable_intr_bank(int pin_out, bool on) index =3D FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out); mask =3D FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out); =20 + guard(raw_spinlock_irqsave)(&pdc->lock); + enable =3D pdc_reg_read(pdc->regs->irq_en_reg, index); __assign_bit(mask, &enable, on); =20 - if (pdc_x1e_quirk) + if (pdc->x1e_quirk) pdc_x1e_irq_enable_write(index, enable); else pdc_reg_write(pdc->regs->irq_en_reg, index, enable); @@ -213,32 +225,15 @@ static void pdc_enable_intr_cfg(int pin_out, bool on) pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, enable); } =20 -static void __pdc_enable_intr(int pin_out, bool on) -{ - if (pdc_version < PDC_VERSION_3_2) - pdc_enable_intr_bank(pin_out, on); - else - pdc_enable_intr_cfg(pin_out, on); -} - -static void pdc_enable_intr(struct irq_data *d, bool on) -{ - unsigned long flags; - - raw_spin_lock_irqsave(&pdc_lock, flags); - __pdc_enable_intr(d->hwirq, on); - raw_spin_unlock_irqrestore(&pdc_lock, flags); -} - static void qcom_pdc_gic_disable(struct irq_data *d) { - pdc_enable_intr(d, false); + pdc->enable_intr(d->hwirq, false); irq_chip_disable_parent(d); } =20 static void qcom_pdc_gic_enable(struct irq_data *d) { - pdc_enable_intr(d, true); + pdc->enable_intr(d->hwirq, true); irq_chip_enable_parent(d); } =20 @@ -350,12 +345,10 @@ static struct irq_chip qcom_pdc_gic_chip =3D { =20 static struct pdc_pin_region *get_pin_region(int pin) { - int i; - - for (i =3D 0; i < pdc_region_cnt; i++) { - if (pin >=3D pdc_region[i].pin_base && - pin < pdc_region[i].pin_base + pdc_region[i].cnt) - return &pdc_region[i]; + for (int i =3D 0; i < pdc->region_cnt; i++) { + if (pin >=3D pdc->region[i].pin_base && + pin < pdc->region[i].pin_base + pdc->region[i].cnt) + return &pdc->region[i]; } =20 return NULL; @@ -411,35 +404,35 @@ static const struct irq_domain_ops qcom_pdc_ops =3D { static int pdc_setup_pin_mapping(struct device *dev) { struct device_node *np =3D dev->of_node; - int ret, n, i; + int ret, n; =20 n =3D of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); if (n <=3D 0 || n % 3) return -EINVAL; =20 - pdc_region_cnt =3D n / 3; - pdc_region =3D devm_kcalloc(dev, pdc_region_cnt, sizeof(*pdc_region), GFP_K= ERNEL); - if (!pdc_region) { - pdc_region_cnt =3D 0; + pdc->region_cnt =3D n / 3; + pdc->region =3D devm_kcalloc(dev, pdc->region_cnt, sizeof(*pdc->region), GF= P_KERNEL); + if (!pdc->region) { + pdc->region_cnt =3D 0; return -ENOMEM; } =20 - for (n =3D 0; n < pdc_region_cnt; n++) { + for (n =3D 0; n < pdc->region_cnt; n++) { ret =3D of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 0, - &pdc_region[n].pin_base); + &pdc->region[n].pin_base); if (ret) return ret; ret =3D of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 1, - &pdc_region[n].parent_base); + &pdc->region[n].parent_base); if (ret) return ret; ret =3D of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 2, - &pdc_region[n].cnt); + &pdc->region[n].cnt); if (ret) return ret; =20 - for (i =3D 0; i < pdc_region[n].cnt; i++) - __pdc_enable_intr(i + pdc_region[n].pin_base, 0); + for (int i =3D 0; i < pdc->region[n].cnt; i++) + pdc->enable_intr(i + pdc->region[n].pin_base, 0); } =20 return 0; @@ -477,12 +470,15 @@ static int qcom_pdc_probe(struct platform_device *pdev,= struct device_node *pare if (pdc->version >=3D PDC_VERSION_3_2) { pdc->cfg_fields =3D &pdc_cfg_v3_2; pdc->regs =3D &pdc_v3_2; + pdc->enable_intr =3D pdc_enable_intr_cfg; } else if (pdc->version >=3D PDC_VERSION_3_0) { pdc->cfg_fields =3D &pdc_cfg_v3_0; pdc->regs =3D &pdc_v3_0; + pdc->enable_intr =3D pdc_enable_intr_bank; } else { pdc->cfg_fields =3D &pdc_cfg_v2_7; pdc->regs =3D &pdc_v2_7; + pdc->enable_intr =3D pdc_enable_intr_bank; } =20 /* @@ -501,7 +497,7 @@ static int qcom_pdc_probe(struct platform_device *pdev, s= truct device_node *pare return -ENXIO; } =20 - pdc_x1e_quirk =3D true; + pdc->x1e_quirk =3D true; } =20 parent_domain =3D irq_find_host(parent); @@ -510,6 +506,8 @@ static int qcom_pdc_probe(struct platform_device *pdev, s= truct device_node *pare return -ENXIO; } =20 + raw_spin_lock_init(&pdc->lock); + ret =3D pdc_setup_pin_mapping(dev); if (ret) { pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);