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Wed, 08 Jul 2026 04:48:16 -0700 (PDT) Received: from brgl-qcom.home ([2a01:cb1d:dc:7e00:6d02:5f1c:554:8e46]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47aa09608d4sm43390968f8f.25.2026.07.08.04.48.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2026 04:48:15 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Linus Walleij , Bartosz Golaszewski , Maulik Shah Cc: Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, Sneh Mankad , Konrad Dybcio , Stephan Gerhold Subject: Re: (subset) [PATCH v4 0/7] x1e80100: Enable PDC wake GPIOs and deepest idle state Date: Wed, 8 Jul 2026 13:48:14 +0200 Message-ID: <178351128411.15863.15352829199730625357.b4-ty@oss.qualcomm.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260707-hamoa_pdc_v3-v4-0-dfd1f4a3ae89@oss.qualcomm.com> References: <20260707-hamoa_pdc_v3-v4-0-dfd1f4a3ae89@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: fLUw8CWBRFswrlZz6xGxauvzIm-jnmG5 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA4MDExNSBTYWx0ZWRfXzABcBTc7Yaop +aOKH1NVa14iUf4RqUZ17aA7LNne8MRvznlrBUEA5OCPa0kj0QyQln3N3rTuDpFc3u0CoA06B0j q+l00IYQbWOxK8hyBD82PcZKB8SPTtc= X-Authority-Analysis: v=2.4 cv=F9JnsKhN c=1 sm=1 tr=0 ts=6a4e3902 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=3rgbGgh808wYF3KoWbcA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-GUID: fLUw8CWBRFswrlZz6xGxauvzIm-jnmG5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA4MDExNSBTYWx0ZWRfX5emao+IzvWKp Q40TIPdvx++weAA+3c36MTrVe48XsqixyOBxd7d8GZi3fSVqfUDno5NDufdB9jzzL8DoN2eVho2 aM12wKA9t13xAccF1IujjV5o7Xa39bB5eBx3IyY6PQLN7EKPoRrOCDBN4cf0e0wj5+y+C3AIIUk UWLw+duFaVSAtn/glo/L8MqA4HSShYyHeO/bRTMFCHH+fGUR1BPDUH8setjy/A0izISI16CXflC XZq5cbY3cnb+iPje0DYPi+DQM8kGpSI2JbZCCcodV7+/4OATBrh+OZRSgmOGyWZTGf90XHeRlMG s1GFkT3tdGM9jCyPmSkNzcs2RPH/tNKlZfCNgTd2orcAvjz9vGY72WZbPHlVx0V7PtZc0W72cA1 KwVoUUEyZ941oNq/RXseZM19XLMTK06o8i+885P03nCmqyd2b+EwuNIdeUV+JWIkSyMam/dr1Vw nPknqG3iueOyJLyeFgg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-08_01,2026-07-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607080115 On Tue, 07 Jul 2026 14:51:32 +0530, Maulik Shah wrote: > There are two modes PDC irqchip can work in > - pass through mode > - secondary controller mode > > Secondary mode is supported depending on SoC using PDC HW Version v3.0 > or higher. > > [...] Applied, thanks! [5/7] pinctrl: qcom: Acknowledge IRQs for PDC interrupt controller https://git.kernel.org/brgl/c/f790ea0b699d95d18572979b1bc1673d8f31eb3c [6/7] Revert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now" https://git.kernel.org/brgl/c/77fbc756d9cbe53a9496cb2c53ae209d37d5af2d Best regards, -- Bartosz Golaszewski