From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1305A32C957; Sat, 11 Jul 2026 19:50:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783799407; cv=none; b=JFGRJtuwX4UeZ5zfdJaIIgdKEHm0NQlyHItlicxHILZU7oyNZOJAJj0bWGfzfx5BZw/c/HZ9R37J7xTQg0ncNOPzRD+Gzk/kqm1ho+r29EOSzMX40ri9sAJyNTEOuy372YOyVrx/58xCvd7X/WVnx/eikbuA0PRZb/mThOYuKY0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783799407; c=relaxed/simple; bh=RQRWcT0CFjSsdkfjLAKCex6QiqQoLY7VOCjbz8nKe5w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HBnPWe07vvZueES/PnZfW0x6sBgq8WN9YlUB4X4zFiseyvcqAjXUH1YVGSVJ3+V7Bv2vqI1SOkaFY7fRTp5Jkhb/66pAFKuyZSTb+HE5hKCfemx7yxZlcPS7Dk55VZwzygvWvDlICjZHVp5XQIOr/dywyMSzWvpAiaMhyS49zHg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=S9xKZS1A; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="S9xKZS1A" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A49431F000E9; Sat, 11 Jul 2026 19:50:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783799405; bh=8MeqxyuSFOsfA7kp2hQbDLGK4Y258AvNZPf0lyCyxsQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=S9xKZS1AxJRSq75MmrZbbaBfjl45aPKS4vPveMu/Eaa0RTSt4MMbBv7RGamjCFgoF /iu6UALf5m3eQZTPuFu+nZHv2xC5AXD5JLoQ2FKXpIb8qi4QVet771OKAb2kgTJM94 cSqFjfogApolQM5CVLth/anoOAOYmVthO6C9bX9cTC5HmP48LYsgjaANqgNHTKsEyy 1NafuQXxAU7yrqdJr3/vuKG4PHzzztfn8OKXLukau0GhP/1Zcr9h0IET2YWgJ8A7VN Y74oWMLTkE8fIISQ5ZiFCVax1ChIqyUFIJsOjPiMS6KgaaUE+5YHvf1vv9VzqDk+hF N5jfRpwUrsi/A== From: Bjorn Andersson To: Suzuki K Poulose , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Konrad Dybcio , Mike Leach , Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio Subject: Re: [PATCH v3 0/3] Enable CTCU and ETR devices for multiple QCOM platforms Date: Sat, 11 Jul 2026 14:49:44 -0500 Message-ID: <178379938589.163099.8612045419740937512.b4-ty@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260204-enable-ctcu-and-etr-v3-0-0bb95c590ae1@oss.qualcomm.com> References: <20260204-enable-ctcu-and-etr-v3-0-0bb95c590ae1@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Wed, 04 Feb 2026 10:22:00 +0800, Jie Gan wrote: > The DT‑binding patch adds platform‑specific compatibles for the > CTCU device, and the following Qualcomm platforms are included: > Kaanapali > Pakala(sm8750) > Hamoa(x1e80100) > Glymur > > [...] Applied, thanks! [1/3] dt-binding: document QCOM platforms for CTCU device commit: 1ab1005cb6beb278df53b23f7cf520b4d6bd56cb [2/3] arm64: dts: qcom: hamoa: enable ETR and CTCU devices commit: f77ef7a6a97eb29020be430d3125e3b0e0e713f8 [3/3] arm64: dts: qcom: sm8750: enable ETR and CTCU devices commit: 55d6c80716b1ceb39fb8143976dfb1dda4e43a2e Best regards, -- Bjorn Andersson