From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 768DA42D744 for ; Thu, 16 Jul 2026 16:48:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784220505; cv=none; b=rf4NnnPo+rgJF0/d1wTLIdk9pdQgqxMWJ8RHR0LNOMsjtrR8G8ia54zuxBwIb7pgnyGsaw5lFadHDrtRzWId0raS/iYYr8ibSpHMsfblh+Vbiq/iGZj03mj/y9IrcwoRjSzq6Y4KIdNlM91Zvvyo/puPSPDi+vYkAgiXRQlQGCg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784220505; c=relaxed/simple; bh=G/Rd2VMFEZRetMyw/0klkRIkFHJ2ecAB2sGGTqKrbY4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tA86OmFG5GIjvk1MXxZn9mmlscbmL5EtU1ilFH+BvJd5Q8MzYnfEvX5aN5/2GAHpkO+fPBQ++0d8+RAQ1rD4Q1d5Ycs/ujlymVbvRsMrQIzafq0B+dOi8502ZItAdLzVWE+9b+yrma32WtFHF6kZ2vR4BjlUc0fsRqDI59nfS60= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Kuzg2Zxj; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Kuzg2Zxj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E0FF81F000E9; Thu, 16 Jul 2026 16:48:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784220493; bh=y1PPfjkTZrp/s64FCNPQUtxdWzbmzNrUHvfHXCt1OSs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Kuzg2ZxjXzvwydEEcUeWm1MQSh6i9G+3YaPFiHE2XsiH7URyHiDAo7HDkngTTLyYP Jc402ebkgfZePpZww4ReGKJOOknt1FFd3lc1m3rFduz7bdAKacgVRTz692C7An7JdI LACJ1GebKP1KYEvMVY7dsbDVkmnFRGTKRGcyqkalhVhKYomu0ukoUohvlsSuvRrbdL uAHpAF2cWyQ8o3408+qUeYlWeqhseYmEoy8rMFTvzos4RPtCN/lZH2El7gYvp0ie8i 45neXIfA9J/8Qe5Y2CxtLmeoL/8XIKR86rIvFtkl/Rmql0PEM0K9ZNCJ4qM5s79wC4 P1rJWnPlCD+Eg== From: Will Deacon To: Ben Horgan , James Morse , Reinette Chatre , Catalin Marinas , Gavin Shan , Shaopeng Tan , Jesse Chick , Fenghua Yu Cc: kernel-team@android.com, Will Deacon , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Matt Ochs Subject: Re: [PATCH] arm_mpam: Fix MPAMCFG_MBW_PBM register setting Date: Thu, 16 Jul 2026 17:47:58 +0100 Message-ID: <178420954768.37480.18364490568749911795.b4-ty@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260607050925.252475-1-fenghuay@nvidia.com> References: <20260607050925.252475-1-fenghuay@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Sat, 06 Jun 2026 22:09:25 -0700, Fenghua Yu wrote: > MPAMCFG_MBW_PBM is written from cfg if cfg has the MBW partition feature. > It is reset when cfg does not have the MBW partition feature. > > But the register handling is reversed. This may cause an incorrect > register setting. For example, during an MPAM reset, reset_cfg is > empty (no MBW partition feature set), and cfg->mbw_pbm is 0. Instead of > resetting MPAMCFG_MBW_PBM to all 1's, the current logic will set it to > cfg->mbw_pbm, which is 0. > > [...] Applied to arm64 (for-next/fixes), thanks! [1/1] arm_mpam: Fix MPAMCFG_MBW_PBM register setting https://git.kernel.org/arm64/c/021118ce5ea9 Cheers, -- Will https://fixes.arm64.dev https://next.arm64.dev https://will.arm64.dev