[tip: x86/cleanups] x86/apic: Ensure ICR register write value is handled as 32 bits

["tip-bot2 for Melody Wang" <tip-bot2@linutronix.de>]

The following commit has been merged into the x86/cleanups branch of tip:

Commit-ID:     cdb4d57c3e497fe99a9ffa54f085b75130b12b5a
Gitweb:        https://git.kernel.org/tip/cdb4d57c3e497fe99a9ffa54f085b75130b12b5a
Author:        Melody Wang <huibo.wang@amd.com>
AuthorDate:    Wed, 08 Jul 2026 01:21:17 
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Mon, 20 Jul 2026 11:58:50 -07:00

x86/apic: Ensure ICR register write value is handled as 32 bits

The low 32-bit ICR data is prepared by __prepare_ICR(), which returns a 32-bit
value. However, when this value is assigned to a new variable, it's easy to
mistakenly declare that variable with a different width.

To avoid this class of mistakes, use __prepare_ICR() directly as the function
argument instead of storing its result in an intermediate variable. This also
shaves off a bunch of lines in the code.

There should be no functionality change resulting from this.

Signed-off-by: Melody Wang <huibo.wang@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260708012117.177959-1-huibo.wang@amd.com
---
 arch/x86/kernel/apic/local.h        | 4 +---
 arch/x86/kernel/apic/x2apic_phys.c  | 4 +---
 arch/x86/kernel/apic/x2apic_savic.c | 5 +----
 3 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/arch/x86/kernel/apic/local.h b/arch/x86/kernel/apic/local.h
index 998efd4..090dd71 100644
--- a/arch/x86/kernel/apic/local.h
+++ b/arch/x86/kernel/apic/local.h
@@ -44,9 +44,7 @@ static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector,
 #ifdef CONFIG_X86_X2APIC
 static inline void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest)
 {
-	unsigned long cfg = __prepare_ICR(0, vector, dest);
-
-	native_x2apic_icr_write(cfg, apicid);
+	native_x2apic_icr_write(__prepare_ICR(0, vector, dest), apicid);
 }
 #endif
 
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index 10f7902..090647c 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -85,11 +85,9 @@ static void
 
 static void __x2apic_send_IPI_shorthand(int vector, u32 which)
 {
-	unsigned long cfg = __prepare_ICR(which, vector, 0);
-
 	/* x2apic MSRs are special and need a special fence: */
 	weak_wrmsr_fence();
-	native_x2apic_icr_write(cfg, 0);
+	native_x2apic_icr_write(__prepare_ICR(which, vector, 0), 0);
 }
 
 void x2apic_send_IPI_allbutself(int vector)
diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2apic_savic.c
index dbc5678..4bc6d7e 100644
--- a/arch/x86/kernel/apic/x2apic_savic.c
+++ b/arch/x86/kernel/apic/x2apic_savic.c
@@ -243,10 +243,7 @@ static void savic_write(u32 reg, u32 data)
 
 static void send_ipi(u32 dest, unsigned int vector, unsigned int dsh)
 {
-	unsigned int icr_low;
-
-	icr_low = __prepare_ICR(dsh, vector, APIC_DEST_PHYSICAL);
-	savic_icr_write(icr_low, dest);
+	savic_icr_write(__prepare_ICR(dsh, vector, APIC_DEST_PHYSICAL), dest);
 }
 
 static void savic_send_ipi(int cpu, int vector)