From: Chen-Yu Tsai <wens@kernel.org>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Andre Przywara <andre.przywara@arm.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ARM: dts: allwinner: a10: Fix PMU interrupt
Date: Thu, 23 Jul 2026 01:29:00 +0800 [thread overview]
Message-ID: <178474134045.3407214.16203991079219097416.b4-ty@kernel.org> (raw)
In-Reply-To: <20260720215128.5761-1-andre.przywara@arm.com>
On Mon, 20 Jul 2026 23:51:28 +0200, Andre Przywara wrote:
> The Performance Monitoring Unit of the Cortex-A8 cores in the Allwinner
> A10 SoC is connected to interrupt line 66, not 3. This is shown in the
> manual (where interrupt 3 is assigned to UART2, also in our .dtsi), but
> has also been confirmed by triggering an PMU overflow interrupt and
> inspecting the IRQ controller status registers (from U-Boot).
> Please note that "perf stat" does not use interrupts, this might explain
> why this evaded the initial testing.
>
> [...]
Applied to sunxi/dt-for-7.3 in sunxi, thanks!
[1/1] ARM: dts: allwinner: a10: Fix PMU interrupt
https://git.kernel.org/sunxi/linux/c/eb7051f75646
Best regards,
--
Chen-Yu Tsai <wens@kernel.org>
prev parent reply other threads:[~2026-07-22 17:29 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-20 21:51 Andre Przywara
2026-07-22 17:29 ` Chen-Yu Tsai [this message]
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