From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9ABF133688C; Sat, 25 Jul 2026 01:40:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784943603; cv=none; b=C2NJqlX4GTaS6rLGFR7/RH0FzQAafo+kPkRFPcSatL2ftPaUGTlqx8ouWkBxBbuQ+fKd8Ox/gcZzdYKxpvrGenK7ii8yfR+5QwHLj7tvfmd0YMeF1JBrRH9BtV22Plh6DBGTe4KxD2gITlD+UH6iH9ySqyoqSXqmPvDXp0SwUd8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784943603; c=relaxed/simple; bh=cvJ8cU1CqXupmB4xYiDTOWoy4nthQTxjltsaoxcm/pk=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=c/jUTNrW+CTV+Q74yHoK6qKz0pKrcZHe6jyz5wCT0cF7MEuS+MUQ92H1jghopNzOoRy/dPqARzYWgGma4u478ZkMfuqvfhcOpbN5R/sPm9RsGdIo8D4yT5N5zOUmDOieO0hLZmuHKd6rwJWeUlx1Vvz6FZnNIuYhFo/6M8r0g5M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=U0+x9i+0; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=qBSl7MWB; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="U0+x9i+0"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="qBSl7MWB" Date: Sat, 25 Jul 2026 01:39:58 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1784943600; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hlkbyTXI8mQTM56PGd1NjgcXjj6nraEJa3grwrNi8no=; b=U0+x9i+0bojOvWkt2ksc2oMZ+c2SxjvGFN2fNc6TRCV+yn/L8WUac77gWqevTDfrFhS+0G oBK0iuT62mU7uYTwv09Sm6RuckFP1I0Pey9rDRLY+rC0RYRyktXwgTPh3xeYSXuM4LziTE orqyniQjcCEXW3ZebqXtxqYFVqsyi8EFVipFI1odty6zwTXvfnV9fTvboLXCg9fM+chik7 NGQi3FfzInbN/JgYZjLHC73msNjbPrKaOIHb/FUYXZ61/q50DFZmc/Z3FPNDKS16W/JHS1 9gtMvWR9a1mFSwmIGL9DVKundyw4/7ct/rZQc5pVOCTZKheyvPJadX9+eW0t6g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1784943600; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hlkbyTXI8mQTM56PGd1NjgcXjj6nraEJa3grwrNi8no=; b=qBSl7MWBuWPP3i9FvmXcahI1qdsMnetBZ2L28rle8q/CV31a0AfsSln+91uwTA3ju8Pujn +BjVXUtVW49WqPBQ== From: "tip-bot2 for Borislav Petkov (AMD)" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] x86/topo: Map vendor CPU types to generic Linux such types Cc: "Borislav Petkov (AMD)" , Vishal Badole , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260721154514.2506972-2-Vishal.Badole@amd.com> References: <20260721154514.2506972-2-Vishal.Badole@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178494359834.112641.6886363392504029354.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 598ebce64c4cfaca54cbecdc25a7ef56ea701051 Gitweb: https://git.kernel.org/tip/598ebce64c4cfaca54cbecdc25a7ef56ea7= 01051 Author: Borislav Petkov (AMD) AuthorDate: Tue, 21 Jul 2026 21:15:12 +05:30 Committer: Borislav Petkov (AMD) CommitterDate: Thu, 23 Jul 2026 14:23:15 -07:00 x86/topo: Map vendor CPU types to generic Linux such types Sashiko reported=C2=B9 that a confusion could ensue if a vendor-specific CPU type 0 (performance) gets attempted to be used in a x86_cpu_id match table. The current logic treats 0 as the wildcard X86_CPU_TYPE_ANY and such a thing would end up matching the wrong CPUs. This is all backwards because we started using the vendor-specific CPU type number instead of using a Linux-defined, generic CPU type which is agnostic. Convert the current logic to it before users start appearing. =C2=B9https://sashiko.dev/#/patchset/20260629094349.533301-1-Vishal.Badole%= 40amd.com Signed-off-by: Borislav Petkov (AMD) Signed-off-by: Vishal Badole Link: https://patch.msgid.link/20260721154514.2506972-2-Vishal.Badole@amd.com --- arch/x86/include/asm/processor.h | 18 ++++++++++++---- arch/x86/include/asm/topology.h | 7 +------ arch/x86/kernel/acpi/cppc.c | 4 +-- arch/x86/kernel/cpu/match.c | 30 +-------------------------- arch/x86/kernel/cpu/topology.h | 1 +- arch/x86/kernel/cpu/topology_amd.c | 6 +++-- arch/x86/kernel/cpu/topology_common.c | 8 +++++-- 7 files changed, 28 insertions(+), 46 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processo= r.h index 87b1d4c..fc0350f 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -68,9 +68,13 @@ extern u16 __read_mostly tlb_lld_2m; extern u16 __read_mostly tlb_lld_4m; extern u16 __read_mostly tlb_lld_1g; =20 -/* - * CPU type and hardware bug flags. Kept separately for each CPU. - */ +enum x86_topology_cpu_type { + /* X86_CPU_TYPE_ANY */ + TOPO_CPU_TYPE_ANY =3D 0, + TOPO_CPU_TYPE_PERFORMANCE, + TOPO_CPU_TYPE_EFFICIENCY, + TOPO_CPU_TYPE_UNKNOWN, +}; =20 struct cpuinfo_topology { // Real APIC ID read from the local APIC @@ -104,7 +108,7 @@ struct cpuinfo_topology { =20 // Hardware defined CPU-type union { - u32 cpu_type; + u32 hw_cpu_type; struct { // CPUID.1A.EAX[23-0] u32 intel_native_model_id :24; @@ -119,8 +123,14 @@ struct cpuinfo_topology { amd_type :4; }; }; + + // Linux vendor-agnostic CPU type + enum x86_topology_cpu_type cpu_type; }; =20 +/* + * CPU type and hardware bug flags. Kept separately for each CPU. + */ struct cpuinfo_x86 { union { /* diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index 8fb61d2..ef76ba6 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -114,12 +114,6 @@ enum x86_topology_domains { TOPO_MAX_DOMAIN, }; =20 -enum x86_topology_cpu_type { - TOPO_CPU_TYPE_PERFORMANCE, - TOPO_CPU_TYPE_EFFICIENCY, - TOPO_CPU_TYPE_UNKNOWN, -}; - struct x86_topology_system { unsigned int dom_shifts[TOPO_MAX_DOMAIN]; unsigned int dom_size[TOPO_MAX_DOMAIN]; @@ -160,7 +154,6 @@ extern unsigned int __num_nodes_per_package; struct cpuinfo_x86; =20 const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c); -enum x86_topology_cpu_type get_topology_cpu_type(struct cpuinfo_x86 *c); =20 static inline unsigned int topology_max_packages(void) { diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index be4c5e9..b8f5dd0 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -241,7 +241,6 @@ EXPORT_SYMBOL_GPL(amd_detect_prefcore); */ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) { - enum x86_topology_cpu_type core_type =3D get_topology_cpu_type(&cpu_data(cp= u)); bool prefcore; int ret; u32 tmp; @@ -273,8 +272,9 @@ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *= numerator) =20 /* detect if running on heterogeneous design */ if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) { - switch (core_type) { + switch (cpu_data(cpu).topo.cpu_type) { case TOPO_CPU_TYPE_UNKNOWN: + case TOPO_CPU_TYPE_ANY: pr_warn("Undefined core type found for cpu %d\n", cpu); break; case TOPO_CPU_TYPE_PERFORMANCE: diff --git a/arch/x86/kernel/cpu/match.c b/arch/x86/kernel/cpu/match.c index 4604802..7ab077f 100644 --- a/arch/x86/kernel/cpu/match.c +++ b/arch/x86/kernel/cpu/match.c @@ -6,34 +6,6 @@ #include =20 /** - * x86_match_vendor_cpu_type - helper function to match the hardware defined - * cpu-type for a single entry in the x86_cpu_id - * table. Note, this function does not match the - * generic cpu-types TOPO_CPU_TYPE_EFFICIENCY and - * TOPO_CPU_TYPE_PERFORMANCE. - * @c: Pointer to the cpuinfo_x86 structure of the CPU to match. - * @m: Pointer to the x86_cpu_id entry to match against. - * - * Return: true if the cpu-type matches, false otherwise. - */ -static bool x86_match_vendor_cpu_type(struct cpuinfo_x86 *c, const struct x8= 6_cpu_id *m) -{ - if (m->type =3D=3D X86_CPU_TYPE_ANY) - return true; - - /* Hybrid CPUs are special, they are assumed to match all cpu-types */ - if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) - return true; - - if (c->x86_vendor =3D=3D X86_VENDOR_INTEL) - return m->type =3D=3D c->topo.intel_type; - if (c->x86_vendor =3D=3D X86_VENDOR_AMD) - return m->type =3D=3D c->topo.amd_type; - - return false; -} - -/** * x86_match_cpu - match current CPU against an array of x86_cpu_ids * @match: Pointer to array of x86_cpu_ids. Last entry terminated with * {}. @@ -81,7 +53,7 @@ const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu= _id *match) continue; if (m->feature !=3D X86_FEATURE_ANY && !cpu_has(c, m->feature)) continue; - if (!x86_match_vendor_cpu_type(c, m)) + if (m->type !=3D X86_CPU_TYPE_ANY && c->topo.cpu_type !=3D m->type) continue; return m; } diff --git a/arch/x86/kernel/cpu/topology.h b/arch/x86/kernel/cpu/topology.h index 3732629..74e02ba 100644 --- a/arch/x86/kernel/cpu/topology.h +++ b/arch/x86/kernel/cpu/topology.h @@ -22,6 +22,7 @@ void topology_set_dom(struct topo_scan *tscan, enum x86_top= ology_domains dom, bool cpu_parse_topology_ext(struct topo_scan *tscan); void cpu_parse_topology_amd(struct topo_scan *tscan); void cpu_topology_fixup_amd(struct topo_scan *tscan); +enum x86_topology_cpu_type get_topology_cpu_type(struct cpuinfo_x86 *c); =20 static inline u32 topo_shift_apicid(u32 apicid, enum x86_topology_domains do= m) { diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topolog= y_amd.c index da080d7..c5a6944 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -177,8 +177,10 @@ static void topoext_fixup(struct topo_scan *tscan) =20 static void parse_topology_amd(struct topo_scan *tscan) { - if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) - tscan->c->topo.cpu_type =3D cpuid_ebx(0x80000026); + if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) { + tscan->c->topo.hw_cpu_type =3D cpuid_ebx(0x80000026); + tscan->c->topo.cpu_type =3D get_topology_cpu_type(tscan->c); + } =20 /* * Try to get SMT, CORE, TILE, and DIE shifts from extended diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topo= logy_common.c index cf75134..b9d025f 100644 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -168,8 +168,12 @@ static void parse_topology(struct topo_scan *tscan, bool= early) case X86_VENDOR_INTEL: if (!IS_ENABLED(CONFIG_CPU_SUP_INTEL) || !cpu_parse_topology_ext(tscan)) parse_legacy(tscan); - if (c->cpuid_level >=3D 0x1a) - c->topo.cpu_type =3D cpuid_eax(0x1a); + + if (c->cpuid_level >=3D 0x1a) { + c->topo.hw_cpu_type =3D cpuid_eax(0x1a); + c->topo.cpu_type =3D get_topology_cpu_type(c); + } + break; } }