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From: Jai Luthra <jai.luthra@ideasonboard.com>
To: Hans de Goede <hansg@kernel.org>, Kate Hsuan <hpa@redhat.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Sakari Ailus <sakari.ailus@linux.intel.com>,
	Serin Yeh <serin.yeh@intel.com>
Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org,
	Kate Hsuan <hpa@redhat.com>
Subject: Re: [PATCH] media: i2c: imx471: Add line length PCK setting
Date: Tue, 28 Jul 2026 10:57:40 +0530	[thread overview]
Message-ID: <178521646078.4139729.8353081240992310969@freya> (raw)
In-Reply-To: <20260728042013.23707-1-hpa@redhat.com>

Hi Kate,

Thank you for the patch.

Quoting Kate Hsuan (2026-07-28 09:50:13)
> Add the line length PCK setting to the IMX471 driver. This parameter
> determines the horizontal line scan duration and is used for
> controlling the frame rate.
> 
> Signed-off-by: Kate Hsuan <hpa@redhat.com>
> ---
>  drivers/media/i2c/imx471.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/media/i2c/imx471.c b/drivers/media/i2c/imx471.c
> index 6d358b11e96d..e661f5b78dcc 100644
> --- a/drivers/media/i2c/imx471.c
> +++ b/drivers/media/i2c/imx471.c
> @@ -91,6 +91,7 @@
>  #define IMX471_CSI_2_LANE_MODE                 1
>  #define IMX471_CSI_4_LANE_MODE                 3
>  
> +#define IMX471_REG_LINE_LENGTH_PCK             CCI_REG16(0x0342)
>  #define IMX471_REG_X_ADD_STA                   CCI_REG16(0x0344)
>  #define IMX471_REG_Y_ADD_STA                   CCI_REG16(0x0346)
>  #define IMX471_REG_X_ADD_END                   CCI_REG16(0x0348)
> @@ -240,6 +241,7 @@ static const struct cci_reg_sequence mode_1928x1088_regs[] = {
>         { CCI_REG8(0x030d), 0x02 },
>         { CCI_REG8(0x030e), 0x00 },
>         { CCI_REG8(0x030f), 0x53 },
> +       { IMX471_REG_LINE_LENGTH_PCK, 5008 },

This does not match the mode->llp value (2328) used for 1928x1088, any idea
why?

Aside from the patch, I also see that the value for the PIXEL_RATE control
is derived using the link-frequency and output bit-depth.

It is likely that the sensor's frame rate depends solely on the LLP and FLL
timing registers, so it should be possible to derive a constant pixel rate
value (for a given PLL configuration) that is independent of link-freq and
bit-depth.

Thanks,
    Jai

>         { IMX471_REG_PLL_MULT_DRIV, IMX471_PLL_DUAL },
>         { CCI_REG8(0x3f4c), 0x81 },
>         { CCI_REG8(0x3f4d), 0x81 },
> -- 
> 2.55.0
> 
>

  reply	other threads:[~2026-07-28  5:27 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-28  4:20 Kate Hsuan
2026-07-28  5:27 ` Jai Luthra [this message]
2026-07-28  6:54   ` Kate Hsuan
2026-07-28  7:51     ` Sakari Ailus
2026-07-28  8:33       ` Kate Hsuan
2026-07-28 12:34         ` Sakari Ailus

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