From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E3814446E1; Wed, 29 Jul 2026 09:55:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785318921; cv=none; b=jGmX1VLuN5XG2mZ0Btkyh4+2R1tbExleE4avRFAlXhp+ty5aCk3J1KDg69NX149aTcJPaus4Qrr96ssvOZmZajn7FYIjyglhWZw6TT5CN3EyR+MIXAN/IJCyVt/Q6AWYpY81b2VFo5vd1+AJRsBdmxqVElepkKcwl+YWKqCFfIE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785318921; c=relaxed/simple; bh=j6z/ca4WHN0a9i44heWQgOeItNX2once2rBVIKpHPzk=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=J7u78gZd+R6nI7GKVNDaQb4al3rncHQA0ihTevVyuLvqxykBKTwnpHI7SHZVErAIhRWSKUoWfC29masX9x9iVkGXQab/RsZG6VxzPVMeNYhM5IhY+sqRAHpGsD0fRDKJlf3xE6WVtmWbK9Ov1IaUvgufVT6Bj3hhit/LyevOg2c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hgAsympl; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=RdX7Pn0J; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hgAsympl"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="RdX7Pn0J" Date: Wed, 29 Jul 2026 09:55:12 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1785318914; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4ikeE40JKHcmDUpq/pBWikyPlQ2ta4FQ5gGVbgDatzc=; b=hgAsymplKckjtmhAq61GJSvtkt2kBVy9iy0phzWIkz0SL6etPlsGXZur8AZHsff/xI6irP 7WwzuEM8u+vToRwfXf2hWfAN33yI/apt3HZezi7DjMWPYx4jDnxz/ApglGJWTUqug2KKkr o+OHzZ5Rc6rY3CIJNjgJRzt4yL0G1U4dPizSfOpfW6WTp3flv4tfmTObRu8bcimUwsAZA4 uKA7JShZ4xg2imQFbr9M+O5W+3mKqycQ+BZ3jlF4aOMUYfd97Ucs3cuYDogMSZK3LiK3qB otc7GCBvfsK701OqdFEgDzc1e8Ip+hUJ4f83kvg03QKS/dOFJQwF5NGoSitCdA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1785318914; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4ikeE40JKHcmDUpq/pBWikyPlQ2ta4FQ5gGVbgDatzc=; b=RdX7Pn0JcH19aqJ2OcJO1D9Z4y0Y0Jzfx15brRaqEMBZPg/WZ6Wb2rc7VIbpeDFmItN1AF VWnIRjQaUuCw+aDw== From: "tip-bot2 for K Prateek Nayak" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: locking/core] riscv/runtime-const: Introduce runtime_const_mask_32() Cc: Samuel Holland , Charlie Jenkins , K Prateek Nayak , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260728052540.4728-6-kprateek.nayak@amd.com> References: <20260728052540.4728-6-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178531891265.112641.4565394699740685507.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the locking/core branch of tip: Commit-ID: 3f0d06613ae58ae09c48915638692d093168abc1 Gitweb: https://git.kernel.org/tip/3f0d06613ae58ae09c48915638692d09316= 8abc1 Author: K Prateek Nayak AuthorDate: Tue, 28 Jul 2026 05:25:37=20 Committer: Peter Zijlstra CommitterDate: Tue, 28 Jul 2026 13:07:15 +02:00 riscv/runtime-const: Introduce runtime_const_mask_32() Futex hash computation requires a mask operation with read-only after init data that will be converted to a runtime constant in the subsequent commit. Introduce runtime_const_mask_32 to further optimize the mask operation in the futex hash computation hot path. Since all the current use-cases are of the form GENMASK(n, 0), with n > 0, following sequence: srli a0, a1, imm slli a0, a0, imm is used for RISC-V where imm =3D (31 - width) to improve instruction density and performance. "The RISC-V Instruction Set Manual, Volume I - Unprivileged Architecture" [1] Sec. 2.4.1 "Integer Register-Immediate Instructions" notes the immediate shift for SRLI and SLLI are 5 bits wide starting at bit #10. __runtime_fixup_shift() is reused to patch the immediate shifts for the two instructions. If a future use case arises that needs to tackle arbitrary mask, consider using: lui a0, 0x12346 # upper; +0x800 then >>12 for correct rounding addi a0, a0, 0x678 # lower 12 bits to patch the 32-bit mask in the asm block and return "__ret & (val)" from runtime_const_mask_32() which allows compiler to further optimize the logical and operation. __runtime_fixup_ptr() already patches a lui + addi sequence which can be reused when the need arises. A possible implementation for this alternate scheme can be found at [2]. Suggested-by: Samuel Holland Suggested-by: Charlie Jenkins Assisted-by: Claude:claude-sonnet-4-5 Signed-off-by: Charlie Jenkins Signed-off-by: K Prateek Nayak Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins Link: https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pd= f [1] Link: https://lore.kernel.org/lkml/20260430094730.31624-6-kprateek.nayak@amd.= com/ [2] Link: https://patch.msgid.link/20260728052540.4728-6-kprateek.nayak@amd.com --- arch/riscv/include/asm/asm.h | 1 +- arch/riscv/include/asm/runtime-const.h | 44 +++++++++++++++++++++++++- 2 files changed, 45 insertions(+) diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h index e9e8ba8..b8bf842 100644 --- a/arch/riscv/include/asm/asm.h +++ b/arch/riscv/include/asm/asm.h @@ -34,6 +34,7 @@ #define SZREG __REG_SEL(8, 4) #define LGREG __REG_SEL(3, 2) #define SRLI __REG_SEL(srliw, srli) +#define SLLI __REG_SEL(slliw, slli) =20 #if __SIZEOF_POINTER__ =3D=3D 8 #ifdef __ASSEMBLER__ diff --git a/arch/riscv/include/asm/runtime-const.h b/arch/riscv/include/asm/= runtime-const.h index 1ce0260..a472ebb 100644 --- a/arch/riscv/include/asm/runtime-const.h +++ b/arch/riscv/include/asm/runtime-const.h @@ -159,6 +159,23 @@ __ret; \ }) =20 +#define runtime_const_mask_32(val, sym) \ +({ \ + u32 __ret; \ + asm_inline(".option push\n\t" \ + ".option norvc\n\t" \ + "1:\t" \ + SLLI " %[__ret],%[__val],12\n\t" \ + SRLI " %[__ret],%[__ret],12\n\t" \ + ".option pop\n\t" \ + ".pushsection runtime_mask_" #sym ",\"a\"\n\t" \ + ".long 1b - .\n\t" \ + ".popsection" \ + : [__ret] "=3Dr" (__ret) \ + : [__val] "r" (val)); \ + __ret; \ +}) + #define runtime_const_init(type, sym) do { \ extern s32 __start_runtime_##type##_##sym[]; \ extern s32 __stop_runtime_##type##_##sym[]; \ @@ -262,6 +279,33 @@ static inline void __runtime_fixup_shift(void *where, un= signed long val) mutex_unlock(&text_mutex); } =20 +static inline void __runtime_fixup_mask(void *where, unsigned long val) +{ + unsigned int width =3D (val) ? __fls(val) + 1 : 0; + + /* + * XXX: Current implementation only supports patching masks of + * form GENMASK(width, 0) (width >=3D 0) using a SRLI + SLLI + * sequence instead of LUI + ADDI + AND sequence to improve + * performance, density, and covers all the current use-cases. + * + * When the need arises to support any generic mask, and this + * BUG_ON() is tripped, consider using a: + * + * lui %[__ret], #imm16 + * addi %[__ret], #imm16 + * + * sequence to load the 32bit const mask, and perform a logical + * and outside the asm block before returning the result. Fixup + * can simply reuse the existing __runtime_fixup_32() to patch + * the LUI + ADDI sequence. + */ + BUG_ON(!val || width > 31 || (GENMASK(width - 1, 0) !=3D val)); + + __runtime_fixup_shift(where, 32 - width); + __runtime_fixup_shift(where + 4, 32 - width); +} + static inline void runtime_const_fixup(void (*fn)(void *, unsigned long), unsigned long val, s32 *start, s32 *end) {