From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6ECB4446F6; Wed, 29 Jul 2026 09:55:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785318924; cv=none; b=piO6ulMDZZGuU49lkRiC6+shqQMmA5XlcdD0qeJ0F4BZ6OUHOo/7w5bd89vbSyAsDUBGO0/XDcDfPnYVAdmgUalAB03I4xruyhgLYO/R9VxvpKKfbbxGsSo9zm4MYOFX1o34yISCg6EXztwVgVNRfUILeE07xG7Govd/0zxcQ8g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785318924; c=relaxed/simple; bh=i6mgHQWz71Mm0UKzIFzzcuwoKgMSmaoN62XJlZXCz3Q=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=dCn7xP1lwRmfqaV/WOcPpyWSINRGaqcrkLQBhEM0e9SfKs7wDFvy29guL/be2Ugp9/mUDY2GOAzV828SSW/5AJXavx6fTTzMT7c4OvHJnUHEO1an2z58qi+7NyLCYmJj3mpBELQgVMqoVGIYsZ1PNf/Lf5FighoyDeXHxU+E/LQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=4HXnvYan; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=72eGvgWC; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="4HXnvYan"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="72eGvgWC" Date: Wed, 29 Jul 2026 09:55:15 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1785318917; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cJ4zQV8Y8Ferh+bQuUyQ+pJC9c5CWde3J1k9N8+KyPM=; b=4HXnvYanrYdCVCmD5Rz6ZKxrwrAVOJIDh7LzO8xRfQdYXiHj9oxHUFI0CxGhuKXClTgzbA arGG1jsvXiAjqDQ0iAdaVmTy0nc3NvgdQIEeOdEdRkIT2vowX23ZTQMyvSYLVc8WOIm2WF 55G/tEGPYGAqdPpbsBGuR+Hul1H9LLZAM9wKr1ymKJNFoS/62gzaPm3yFyMteJZa7Gt3ZC SNXZSnFisXU6Ypk1Ty5Z22p8y4ytm/WEC9FrZvM03wMjH/fF1kEVdBR8fw4E7vKbqGo3MT bUCLI26254p9/Ydunmb3ZiBkWUQDxSCPyuzImkBmLAZKavqw2vBS6AtqLWmwVQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1785318917; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cJ4zQV8Y8Ferh+bQuUyQ+pJC9c5CWde3J1k9N8+KyPM=; b=72eGvgWC5WZylVV52fZq6PW4GO0nK4Cegn7kzB390eLkd2pDA6Mpg2o4fTnONMB2sPAI2P 4xyDOJ3ZCGbRYOCQ== From: "tip-bot2 for K Prateek Nayak" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: locking/core] arm64/runtime-const: Introduce runtime_const_mask_32() Cc: Samuel Holland , Charlie Jenkins , K Prateek Nayak , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260728052540.4728-4-kprateek.nayak@amd.com> References: <20260728052540.4728-4-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178531891567.112641.2974963913727588735.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the locking/core branch of tip: Commit-ID: 7eccf137dc044c802f11d3d60bc7fc29066fdf92 Gitweb: https://git.kernel.org/tip/7eccf137dc044c802f11d3d60bc7fc29066= fdf92 Author: K Prateek Nayak AuthorDate: Tue, 28 Jul 2026 05:25:35=20 Committer: Peter Zijlstra CommitterDate: Tue, 28 Jul 2026 13:07:14 +02:00 arm64/runtime-const: Introduce runtime_const_mask_32() Futex hash computation requires a mask operation with read-only after init data that will be converted to a runtime constant in the subsequent commit. Introduce runtime_const_mask_32 to further optimize the mask operation in the futex hash computation hot path. Since all the current use-cases are of the form GENMASK(n, 0), with n > 0, a single: ubfx w0, w0, #0, #widthm1 // w0 =3D w0 [widthm1:0] instruction is used for amd64 to improve instruction dinsity and performance. "Arm A-profile A64 Instruction Set Architecture" manual, Sec. "A64 -- Base Instructions" [1] for UBFX instruction highlights the immediate "width" is encoded as width minus 1 in imms (Bits [15:10]) which is patched by __runtime_fixup_mask() once the mask is known. If a future use case arises that needs to tackle arbitrary mask, consider using: movz w1, #lo16, lsl #0 movk w1, #hi16, lsl #16 to patch the 32-bit mask in the asm block and return "__ret & (val)" from runtime_const_mask_32() which allows compiler to further optimize the logical and operation. __runtime_fixup_ptr() already patches a "movz, + movk lsl #16" sequence which can be reused when the need arises. A possible implementation for this alternate scheme can be found at [2]. Suggested-by: Samuel Holland Suggested-by: Charlie Jenkins Assisted-by: Claude:claude-sonnet-4-6 Signed-off-by: K Prateek Nayak Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins Link: https://developer.arm.com/documentation/ddi0602/2026-03/Base-Instructio= ns/ [1] Link: https://lore.kernel.org/lkml/20260430094730.31624-4-kprateek.nayak@amd.= com/ [2] Link: https://patch.msgid.link/20260728052540.4728-4-kprateek.nayak@amd.com --- arch/arm64/include/asm/runtime-const.h | 46 +++++++++++++++++++++++++- 1 file changed, 46 insertions(+) diff --git a/arch/arm64/include/asm/runtime-const.h b/arch/arm64/include/asm/= runtime-const.h index 838145b..e221a86 100644 --- a/arch/arm64/include/asm/runtime-const.h +++ b/arch/arm64/include/asm/runtime-const.h @@ -36,6 +36,17 @@ :"r" (0u+(val))); \ __ret; }) =20 +#define runtime_const_mask_32(val, sym) ({ \ + unsigned long __ret; \ + asm_inline("1:\t" \ + "ubfx %w0, %w1, #0, #32\n\t" \ + ".pushsection runtime_mask_" #sym ",\"a\"\n\t" \ + ".long 1b - .\n\t" \ + ".popsection" \ + :"=3Dr" (__ret) \ + :"r" (0u+(val))); \ + __ret; }) + #define runtime_const_init(type, sym) do { \ extern s32 __start_runtime_##type##_##sym[]; \ extern s32 __stop_runtime_##type##_##sym[]; \ @@ -73,6 +84,41 @@ static inline void __runtime_fixup_shift(void *where, unsi= gned long val) aarch64_insn_patch_text_nosync(p, insn); } =20 +static inline void __runtime_fixup_mask(void *where, unsigned long val) +{ + unsigned int width =3D (val) ? __fls(val) + 1 : 0; + __le32 *p =3D where; + u32 insn; + + /* + * XXX: Current implementation only supports patching masks of + * form GENMASK(n, 0) (n >=3D 0) using a single UBFX instruction + * to improve performance, density, and covers all the current + * use-cases. + * + * When the need arises to support any generic mask, and this + * BUG_ON() is tripped, consider using a: + * + * movz %w0, #imm16 + * movk %w0, #imm16, lsl #16 + * + * sequence to load the 32bit const mask, and perform a logical + * and outside the asm block before returning the result. Fixup + * can simply reuse the existing __runtime_fixup_16() to patch + * the individual mov instructions. + */ + BUG_ON(!val || width > 32 || (GENMASK(width - 1, 0) !=3D val)); + + /* + * The width of the mask is encoded as (width - 1) in imms + * which is 6 bits starting at bit #10. + */ + insn =3D le32_to_cpu(*p); + insn &=3D 0xffff03ff; + insn |=3D ((width - 1) & 0x1f) << 10; + aarch64_insn_patch_text_nosync(p, insn); +} + static inline void runtime_const_fixup(void (*fn)(void *, unsigned long), unsigned long val, s32 *start, s32 *end) {