From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5470C1459FA; Wed, 29 Jul 2026 09:55:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785318927; cv=none; b=XOCJCsFR7whOTggyIzIw6ILsMw6mAy669+wJZpWOD/WKPebpFjtqFfdTt7NB0fNYdG8sYLEMkFAAIbHuBgXtdZFvtzbl5w5B3x8wA3QVssAq9S6D85Dz59AdTNMKBNO+z5dw9XeRd8HgpuKbcuemXLesFP+JfMk3HbY385teT6Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785318927; c=relaxed/simple; bh=sv3Qybk/imZlhM8B9x454kpYLhQlkJ+IBl3Ibbhk4Jg=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=CUb8gdv2+wpfd2hOZU78mn3j6nUi6FLKFC5qDdt7n4rF0vRc7Yf7OS2WcwBaYfFiclPQcFJKpTTlLqUoCbkAB7a0ZY7l0PYTQM6MlMGAWxJREERaDoFTFJeZVCQ282olosZUhMO/nXM+unTSSzJrE7Bvqh+JcUI5/Qt1OCGVkmg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=nXhLvOC4; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=WE8dZpET; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="nXhLvOC4"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="WE8dZpET" Date: Wed, 29 Jul 2026 09:55:17 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1785318918; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=p3P0b1cAayEw/CmwuLdaC2UQdypB8eg6983D+T3yg+8=; b=nXhLvOC4iD/ixB/ZISXzNlJwlJk9RFJPgiF2iaivpAEyEyq0XXWHIQJj1gyV5GU6gxCn2l 6XvqF4XtW6OfZ3Xy/JGKklwRpQwl6Z6XPTdCqO5qDlRMz2u8gvWQ1KgufwfT8ZIksN/WPX a4zkpFkBd23LojpcYX14mCH9Yk6jA47D9anw/tMw5z3WORCcW9SeJwdYplWn1oASU27BwY 5yXxw3xnTUUt0T4rL4zVzoMqDQkyWnB2ZPqEsnzmO5tFl+hwlgXf4NzAaLSq2RTO66tJ54 jFACs+9b6+MzaKizkv2Df9/QFxuwIAtKoY0pw7CcUa7uiokUIlZWplIEBOjKuA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1785318918; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=p3P0b1cAayEw/CmwuLdaC2UQdypB8eg6983D+T3yg+8=; b=WE8dZpETvFYHi2IDyITIFJFadgbBuiRTtN5BNn1u00qDbwoA9Wytb97GItPpPAlt/Yq5tw c5Lmy24w3YT9Z8Aw== From: "tip-bot2 for K Prateek Nayak" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: locking/core] arm64/runtime-const: Use aarch64_insn_patch_text_nosync() for patching Cc: K Prateek Nayak , "Peter Zijlstra (Intel)" , Catalin Marinas , Charlie Jenkins , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20260728052540.4728-3-kprateek.nayak@amd.com> References: <20260728052540.4728-3-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178531891724.112641.9549636196430358565.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the locking/core branch of tip: Commit-ID: a6690350a4ae7558b39d15fcc776c4d1ab5bbf39 Gitweb: https://git.kernel.org/tip/a6690350a4ae7558b39d15fcc776c4d1ab5= bbf39 Author: K Prateek Nayak AuthorDate: Tue, 28 Jul 2026 05:25:34=20 Committer: Peter Zijlstra CommitterDate: Tue, 28 Jul 2026 13:07:14 +02:00 arm64/runtime-const: Use aarch64_insn_patch_text_nosync() for patching The current scheme to directly patch the kernel text for runtime constants runs into the following issue with futex adapted to using runtime constants on arm64: Unable to handle kernel write to read-only memory at virtual address ... The pc points to the *p assignment in the following call chain: futex_init() runtime_const_init(shift, __futex_shift) __runtime_fixup_shift() *p =3D cpu_to_le32(insn); which suggests that core_initcall() is too late to patch the kernel text directly unlike the "d_hash_shift" which is initialized during vfs_caches_init_early() before the protections are in place. Use aarch64_insn_patch_text_nosync() to patch the runtime constants instead of doing it directly to allow runtime_const_init() slightly later into the boot. Since aarch64_insn_patch_text_nosync() calls caches_clean_inval_pou() internally, __runtime_fixup_caches() ends up being redundant. runtime_const_init() are rare and the overheads of multiple calls to caches_clean_inval_pou() instead of batching them together should be negligible in practice. The cpu_to_le32() conversion of instruction isn't necessary since it is handled later in the aarch64_insn_patch_text_nosync() call-chain: aarch64_insn_patch_text_nosync(addr, insn) aarch64_insn_write(addr, insn) __aarch64_insn_write(addr, cpu_to_le32(insn)) Sashiko noted that aarch64_insn_patch_text_nosync() does not expect a lm_alias() address and Catalin suggested it is safe to drop the lm_alias() for runtime patching since the kernel text is readable. The address passed to fixup function is interpreted as a __le32 and dereferenced as is to read the opcode at the patch site. No functional changes are intended. Signed-off-by: K Prateek Nayak Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Catalin Marinas Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins Link: https://patch.msgid.link/20260728052540.4728-3-kprateek.nayak@amd.com --- arch/arm64/include/asm/runtime-const.h | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/runtime-const.h b/arch/arm64/include/asm/= runtime-const.h index c3dbd3a..838145b 100644 --- a/arch/arm64/include/asm/runtime-const.h +++ b/arch/arm64/include/asm/runtime-const.h @@ -7,6 +7,7 @@ #endif =20 #include +#include =20 /* Sigh. You can still run arm64 in BE mode */ #include @@ -50,34 +51,26 @@ static inline void __runtime_fixup_16(__le32 *p, unsigned= int val) u32 insn =3D le32_to_cpu(*p); insn &=3D 0xffe0001f; insn |=3D (val & 0xffff) << 5; - *p =3D cpu_to_le32(insn); -} - -static inline void __runtime_fixup_caches(void *where, unsigned int insns) -{ - unsigned long va =3D (unsigned long)where; - caches_clean_inval_pou(va, va + 4*insns); + aarch64_insn_patch_text_nosync(p, insn); } =20 static inline void __runtime_fixup_ptr(void *where, unsigned long val) { - __le32 *p =3D lm_alias(where); + __le32 *p =3D where; __runtime_fixup_16(p, val); __runtime_fixup_16(p+1, val >> 16); __runtime_fixup_16(p+2, val >> 32); __runtime_fixup_16(p+3, val >> 48); - __runtime_fixup_caches(where, 4); } =20 /* Immediate value is 6 bits starting at bit #16 */ static inline void __runtime_fixup_shift(void *where, unsigned long val) { - __le32 *p =3D lm_alias(where); + __le32 *p =3D where; u32 insn =3D le32_to_cpu(*p); insn &=3D 0xffc0ffff; insn |=3D (val & 63) << 16; - *p =3D cpu_to_le32(insn); - __runtime_fixup_caches(where, 1); + aarch64_insn_patch_text_nosync(p, insn); } =20 static inline void runtime_const_fixup(void (*fn)(void *, unsigned long),