From: "Rob Herring (Arm)" <robh@kernel.org>
To: Yu-Chien Peter Lin <peter.lin@sifive.com>
Cc: guodong@riscstar.com, pjw@kernel.org, zhangchunyan@iscas.ac.cn,
conor+dt@kernel.org, greentime.hu@sifive.com,
robin.randhawa@sifive.com, dfustini@oss.tenstorrent.com,
raymond.mao@riscstar.com, dave.patel@riscstar.com,
pincheng.plct@isrc.iscas.ac.cn, linux-kernel@vger.kernel.org,
darshan.prajapati@einfochips.com,
linux-riscv@lists.infradead.org, junhui.liu@pigmoral.tech,
akpm@linux-foundation.org, dlan@kernel.org, jim.shu@sifive.com,
devicetree@vger.kernel.org, luxu.kernel@bytedance.com,
krzk+dt@kernel.org, zong.li@sifive.com, anup@brainfault.org,
michal.simek@amd.com, scott@riscstar.com, alex@ghiti.fr,
samuel.holland@sifive.com, aou@eecs.berkeley.edu,
pawandeep.oza@oss.qualcomm.com, palmer@dabbelt.com,
nick.hu@sifive.com
Subject: Re: [PATCH v2 3/3] dt-bindings: sifive: Add WorldGuard Checker
Date: Wed, 29 Jul 2026 13:07:00 -0500 [thread overview]
Message-ID: <178534841831.3259884.2854898669055783798.robh@kernel.org> (raw)
In-Reply-To: <20260729163908.249838-4-peter.lin@sifive.com>
On Thu, 30 Jul 2026 00:39:08 +0800, Yu-Chien Peter Lin wrote:
> Add YAML binding schema for the SiFive wgChecker, a programmable
> access controller integrated in the interconnect fabric of RISC-V
> Worlds-capable SoCs.
>
> wgChecker enforces World ID (WID) based access control on downstream
> bus transactions. Each checker slot encodes a 2-bit permission field
> per WID (read/write), enabling fine-grained memory partitioning and
> device isolation between execution contexts. Violations are reported
> via bus errors, interrupts, or both, selectable and lockable per slot.
>
> The binding registers wgChecker as an access-controllers provider.
> Consumers (i.e. its protected device) reference it via the standard
> access-controllers phandle to declare their access requirements.
>
> Also document the sifive,trustedwid property for the /cpus node,
> identifying the privileged WID authorized to configure all checkers
> on the platform.
>
> Link: https://github.com/riscvarchive/security/blob/main/papers/worldguard%20proposal.pdf
> Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
> Reviewed-by: Zong Li <zong.li@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> ---
> .../devicetree/bindings/riscv/worlds.yaml | 9 +
> .../bindings/sifive/sifive,wgchecker2.yaml | 356 ++++++++++++++++++
> 2 files changed, 365 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/sifive/sifive,wgchecker2.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/sifive/sifive,wgchecker2.example.dtb: uart@1c1000 (ns16550a): $nodename:0: 'uart@1c1000' does not match '^serial(@.*)?$'
from schema $id: http://devicetree.org/schemas/serial/8250.yaml
Documentation/devicetree/bindings/sifive/sifive,wgchecker2.example.dtb: uart@1c1000 (ns16550a): Unevaluated properties are not allowed ('access-controllers', 'reg-names' were unexpected)
from schema $id: http://devicetree.org/schemas/serial/8250.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260729163908.249838-4-peter.lin@sifive.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
next prev parent reply other threads:[~2026-07-29 18:07 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-29 16:39 [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions Yu-Chien Peter Lin
2026-08-10 16:25 ` Conor Dooley
2026-08-11 2:23 ` Yu-Chien Peter Lin
2026-08-11 8:24 ` Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 2/3] dt-bindings: riscv: Add Worlds per-hart properties Yu-Chien Peter Lin
2026-07-29 18:06 ` Rob Herring (Arm)
2026-08-07 7:57 ` Yu-Chien Peter Lin
2026-07-30 7:30 ` Krzysztof Kozlowski
2026-08-11 9:31 ` Yu-Chien Peter Lin
2026-07-29 16:39 ` [PATCH v2 3/3] dt-bindings: sifive: Add WorldGuard Checker Yu-Chien Peter Lin
2026-07-29 18:07 ` Rob Herring (Arm) [this message]
2026-08-11 9:36 ` Yu-Chien Peter Lin
2026-07-30 7:35 ` Krzysztof Kozlowski
2026-07-30 7:37 ` Krzysztof Kozlowski
2026-08-11 9:42 ` Yu-Chien Peter Lin
2026-07-30 17:36 ` Conor Dooley
2026-08-11 9:59 ` Yu-Chien Peter Lin
2026-08-11 9:41 ` Yu-Chien Peter Lin
2026-07-31 1:43 ` [PATCH v2 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Nick Kossifidis
2026-08-04 8:25 ` Yu-Chien Peter Lin
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