From: Bjorn Andersson <andersson@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Taniya Das <taniya.das@oss.qualcomm.com>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Jingyi Wang <jingyi.wang@oss.qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: qcom: Fix camera rivian PLL configuration settings
Date: Mon, 10 Aug 2026 13:45:58 -0500 [thread overview]
Message-ID: <178638756042.656675.10550174478318858559.b4-ty@kernel.org> (raw)
In-Reply-To: <20260801-cam-rivian-pll-config-fix-v1-1-6918d58cd823@oss.qualcomm.com>
On Sat, 01 Aug 2026 01:15:07 +0530, Jagadeesh Kona wrote:
> clk_alpha_pll_write_config() in the PLL configure function skips writes
> to PLL registers when the configured value is 0. However, hardware
> requires USER_CTL_U and CONFIG_CTL_U2 to be explicitly programmed to 0
> for a few rivian PLLs.
>
> Add a clk_regs_configure() callback to ensure these rivian PLL registers
> are correctly initialized on Glymur, SM8750, and Kaanapali platforms.
>
> [...]
Applied, thanks!
[1/1] clk: qcom: Fix camera rivian PLL configuration settings
commit: c4b84911eac4493f7b6639cb9d109a768f1dd4af
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
next prev parent reply other threads:[~2026-08-10 18:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-31 19:45 Jagadeesh Kona
2026-08-01 14:38 ` Taniya Das
2026-08-10 18:45 ` Bjorn Andersson [this message]
2026-08-19 10:47 ` Konrad Dybcio
2026-09-29 3:14 ` Bjorn Andersson
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