From: Oliver Upton <oupton@kernel.org>
To: maz@kernel.org, fuad.tabba@linux.dev, joey.gouly@arm.com,
seiden@linux.ibm.com, suzuki.poulose@arm.com,
yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org,
jic23@kernel.org, Kajetan Puchalski <kajetan.puchalski@arm.com>
Cc: Oliver Upton <oupton@kernel.org>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
stable@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] KVM: arm64: vgic: Fix detection of MI on no pending LR
Date: Wed, 12 Aug 2026 23:49:42 -0700 [thread overview]
Message-ID: <178660378191.666424.10998670140107835415.b4-ty@kernel.org> (raw)
In-Reply-To: <20260810102923.2426475-2-kajetan.puchalski@arm.com>
On Mon, 10 Aug 2026 11:29:24 +0100, Kajetan Puchalski wrote:
> As per the ARM GICv3 spec, the maintenance interrupt identified by
> ICH_MISR_EL2.NP is asserted when it is enabled and no List register is
> in pending state. This is further described in the document as "no List
> registers with the State field set to 0b01 (pending)". By checking only
> the pending bit of the LR (bit 62), KVM currently asserts the MI when
> there are no LRs in "pending" or "pending and active" states.
> Fix the detection logic to consider only the "pending" state.
>
> [...]
Applied to next, thanks!
[1/1] KVM: arm64: vgic: Fix detection of MI on no pending LR
https://git.kernel.org/kvmarm/kvmarm/c/a342faadc5ac
--
Best,
Oliver
prev parent reply other threads:[~2026-08-13 6:49 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-10 10:29 Kajetan Puchalski
2026-08-10 11:32 ` Marc Zyngier
2026-08-13 6:49 ` Oliver Upton [this message]
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