From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7E1A3E16A8; Thu, 20 Aug 2026 08:25:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787214359; cv=none; b=ksLsVBRepblWm/AhGBtNk38lKcIgeGzJSmK54EpfIiXD7KXQGOC3vtq3x4E1ecouuz1rnSBronEvMG2yFgwDIzzs9XddicrpPsZD2E/C9YuFGjCXgZ73EKchcJ38PBeLkXaI7ySFod4MpPfVBfZj5hTroDs/zdWmqMGFuaIu2Ls= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787214359; c=relaxed/simple; bh=M+utD6gg4TmwQUl16qvrgy6Yn5400EQdWH3VzpGS/h4=; h=Date:From:To:Subject:Cc:In-Reply-To:References:MIME-Version: Message-ID:Content-Type; b=NB37xiRngi8VyOyaGuozLbxjiXcXrBekMFwr6fOxwRhJEC96eEbFTrbAe1329nUOtuZ88i6/fozZm0+VgPRvE3b5b+dImOldMGdr+O8IuwQVa4qrVuwAXZndUAATLUvVmjKlCSQKWtllRUZ3/nBo4udeHRMMo/04oNlXQi588kw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Tptkteow; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=mIzcI+Yt; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Tptkteow"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="mIzcI+Yt" Date: Thu, 20 Aug 2026 08:25:54 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1787214356; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=heuDFHvL8nHnTM8LhsHks9NBCY1mHrT/z2wa2E8Gcrw=; b=TptkteowHOogCGFEKG0IpYHQu20OPEaUccFal/4WnhvkRo/eAqbQcxjvdNvpVVGrwbUePO 4GHt80Rs0sF/+c1QIX+4FdxZlHdPTgxKaEdByK6N4Fm+9AMOlY/ooieFL2K/rcmhLGzkzt y/gIDXtEuOpY8Lco7JUa7BVdkT9R5lA1XAGJOyC1SDYkxD98/ooXTM1Yos8hUNrcHuTgdN 81NpKjFqBUzQt32VIauVunaWqok5HHDy5n18hhfngbh09GsIf38tSjGsE4XMC3RdpJwGQ9 G6NpRvcro9h1bSKwiA2Jfbf0pYh1am1CK2lom4uZpUCjZUMWdwEyfba0kmT+vg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1787214356; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=heuDFHvL8nHnTM8LhsHks9NBCY1mHrT/z2wa2E8Gcrw=; b=mIzcI+Ytl/sqQ3Oy/gBd3mSdx837wwriBBhkISk3Y+mxS8d6RTVUlSk4rkwPyCUtIa0b9t 8zabKQL9Wucj+bDQ== From: "tip-bot2 for Sascha Bischoff" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/urgent] irqchip/gic-v5: Synchronize CPU interface disable Cc: Sascha Bischoff , Thomas Gleixner , Lorenzo Pieralisi , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20260811152630.942023-3-sascha.bischoff@arm.com> References: <20260811152630.942023-3-sascha.bischoff@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <178721435461.1542179.17334581464450746491.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Precedence: bulk Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The following commit has been merged into the irq/urgent branch of tip: Commit-ID: ac6db0e0bee18cd4385418c752a007e1aba4ec14 Gitweb: https://git.kernel.org/tip/ac6db0e0bee18cd4385418c752a007e1aba= 4ec14 Author: Sascha Bischoff AuthorDate: Tue, 11 Aug 2026 15:27:31=20 Committer: Thomas Gleixner CommitterDate: Thu, 20 Aug 2026 10:23:53 +02:00 irqchip/gic-v5: Synchronize CPU interface disable The write disabling the GICv5 CPU interface is only guaranteed to take effect after a context synchronization event. Without one, execution can return from gicv5_cpu_disable_interrupts() while an interrupt is still able to be taken. Add an ISB after the ICC_CR0_EL1 write to ensure interrupts are disabled before the function returns. No corresponding ISB is added when enabling the interface, as interrupt delivery is asynchronous and there is no obvious benefit to waiting for it. Fixes: 7ec80fb3f025 ("irqchip/gic-v5: Add GICv5 PPI support") Signed-off-by: Sascha Bischoff Signed-off-by: Thomas Gleixner Reviewed-by: Lorenzo Pieralisi Link: https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff= @arm.com?part=3D6 Link: https://patch.msgid.link/20260811152630.942023-3-sascha.bischoff@arm.com --- drivers/irqchip/irq-gic-v5.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c index 5dcf404..ca48c8b 100644 --- a/drivers/irqchip/irq-gic-v5.c +++ b/drivers/irqchip/irq-gic-v5.c @@ -983,6 +983,7 @@ static void gicv5_cpu_disable_interrupts(void) =20 cr0 =3D FIELD_PREP(ICC_CR0_EL1_EN, 0); write_sysreg_s(cr0, SYS_ICC_CR0_EL1); + isb(); } =20 static void gicv5_cpu_enable_interrupts(void)