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[82.67.6.57]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-486eb35f3d9sm33532218f8f.35.2026.09.15.05.42.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 05:42:06 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: Re: [PATCH v14 06/11] clk: realtek: Add support for gate clock From: Jerome Brunet To: Yu-Chun Lin Cc: sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, cylee12@realtek.com, afaerber@suse.com, jyanchou@realtek.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-realtek-soc@lists.infradead.org, james.tai@realtek.com, cy.huang@realtek.com, stanley_chang@realtek.com, Brian Masney In-Reply-To: <20260901072446.2563145-7-eleanor.lin@realtek.com> References: <20260901072446.2563145-1-eleanor.lin@realtek.com> <20260901072446.2563145-7-eleanor.lin@realtek.com> Date: Tue, 15 Sep 2026 14:42:04 +0200 Message-Id: <178947612411.448573.8319851834736456413.b4-reply@b4> X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6855; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=582/7s3JxsfQWjUN6EMHISrALdyatqiIyfqpimTuSgs=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBqqT0c9mkExB03yY3YHr0fhg3XGhRRzOgE7qYbx W7L0HKibU6JAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaqk9HAAKCRDm/A8cN/La hUCHD/wLct30ewH+5Y3QuClGJamgZYobFou8PoCe8ZNwegUjci+LL8dHd3LcPTENTfOHXYFlgkQ PVDdSqnMGkiIKdJ+TaI92nbPkyt10u920xrR5yGCGE+qZ/wPHxlqjBu6zRUo47KLDJUEGbL7D48 +anKtOEZ3A08V2uIO6RiH/2UsE8JJvAZHVeY0u2K84trqjeBp1DiQe/JSTEAGiSHTjA8ZttkIe3 25FEOUjZ+pbm8G4MeN7gvS2VjLogBvQtHlc90hdCcViOgPqP5SrOcodAOFVeaFuZKTLjbOH6aXO QhBHsQqscoL9OJiDBDe+l22fRIMiCPvDS0pwoeZC48RrFRuGikqcqk4GWCRqHEltrxgh/d31Gly g7BVtv5s+ZSnyHL4p95rVQUNzzc3uAiQ8Llp3hOVayemE/TWZP4BRMLdrSPVgYAvs/yuJyFTK3l FBAYULGRs2mxJmlEhjcOtyjTJDBw+6qsx8YOpgJIeawB3NBo3sM/Pw9/1D4LIfm2e69modjwPRb l7WAxge1vw+kHz8c/yeIII68hVKqg0fBgEKVxUi8oIysPoL8BVtFt+NefV0TSDcNnt/CEMy3BtM Ykad0qE9ldVDgxCCcebuqZMX1e/zfwRqnnJWIciP7QPGLBsUl+CVPgyvX8Aam+s6F5neGVnQO/r SjATklyYSJCn07g== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 On 2026-09-01 15:24 +0800, Yu-Chun Lin wrote: > From: Cheng-Yu Lee > > Introduce clk_regmap_gate_ops supporting enable, disable, is_enabled, and > for standard regmap gate clocks. > > Add clk_regmap_gate_ro_ops as a read-only variant exposing only is_enabled. > > Signed-off-by: Cheng-Yu Lee > Co-developed-by: Yu-Chun Lin > Reviewed-by: Brian Masney > Signed-off-by: Yu-Chun Lin > --- > Changes in v14: > - Move Reviewed-by tag to the correct position. > --- > drivers/clk/realtek/Makefile | 1 + > drivers/clk/realtek/clk-regmap-gate.c | 70 +++++++++++++++++++++++++++ > drivers/clk/realtek/clk-regmap-gate.h | 65 +++++++++++++++++++++++++ > 3 files changed, 136 insertions(+) > create mode 100644 drivers/clk/realtek/clk-regmap-gate.c > create mode 100644 drivers/clk/realtek/clk-regmap-gate.h > > diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile > index 71edc18121c6..840aff067b61 100644 > --- a/drivers/clk/realtek/Makefile > +++ b/drivers/clk/realtek/Makefile > @@ -3,4 +3,5 @@ obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o > > clk-rtk-y += clk-rtk-common.o > clk-rtk-y += clk-pll.o > +clk-rtk-y += clk-regmap-gate.o > clk-rtk-y += freq_table.o > diff --git a/drivers/clk/realtek/clk-regmap-gate.c b/drivers/clk/realtek/clk-regmap-gate.c > new file mode 100644 > index 000000000000..1c32a87d97df > --- /dev/null > +++ b/drivers/clk/realtek/clk-regmap-gate.c > @@ -0,0 +1,70 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation > + * Author: Cheng-Yu Lee > + */ > + > +#include > +#include > +#include > +#include > +#include "clk-regmap-gate.h" > + > +static int rtk_clk_regmap_gate_enable(struct clk_hw *hw) > +{ > + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); > + unsigned int mask; > + unsigned int val; > + > + mask = BIT(clkg->bit_idx); > + val = BIT(clkg->bit_idx); > + > + if (clkg->write_en) { > + mask |= BIT(clkg->bit_idx + 1); > + val |= BIT(clkg->bit_idx + 1); > + } > + > + return regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); > +} > + > +static void rtk_clk_regmap_gate_disable(struct clk_hw *hw) > +{ > + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); > + unsigned int mask; > + unsigned int val; > + > + mask = BIT(clkg->bit_idx); > + val = 0; > + > + if (clkg->write_en) { > + mask |= BIT(clkg->bit_idx + 1); > + val |= BIT(clkg->bit_idx + 1); > + } Could add a comment explaining this write_en thing ? Some kind of volatile bit to commit the change ? > + > + regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); Nitpick: the 2 functions above more less copy/paste. > +} > + > +static int rtk_clk_regmap_gate_is_enabled(struct clk_hw *hw) > +{ > + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); > + int ret; > + u32 val; > + > + ret = regmap_read(clkg->clkr.regmap, clkg->gate_ofs, &val); > + if (ret < 0) > + return ret; > + > + return !!(val & BIT(clkg->bit_idx)); > +} > + > +const struct clk_ops rtk_clk_regmap_gate_ops = { > + .enable = rtk_clk_regmap_gate_enable, > + .disable = rtk_clk_regmap_gate_disable, > + .is_enabled = rtk_clk_regmap_gate_is_enabled, > +}; > +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ops, "CLK_REALTEK"); > + > +const struct clk_ops rtk_clk_regmap_gate_ro_ops = { > + .is_enabled = rtk_clk_regmap_gate_is_enabled, > +}; > +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ro_ops, "CLK_REALTEK"); > diff --git a/drivers/clk/realtek/clk-regmap-gate.h b/drivers/clk/realtek/clk-regmap-gate.h > new file mode 100644 > index 000000000000..9303adda3166 > --- /dev/null > +++ b/drivers/clk/realtek/clk-regmap-gate.h > @@ -0,0 +1,65 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation > + * Author: Cheng-Yu Lee > + */ > + > +#ifndef __CLK_REALTEK_CLK_REGMAP_GATE_H > +#define __CLK_REALTEK_CLK_REGMAP_GATE_H > + > +#include "clk-rtk-common.h" > + > +struct rtk_clk_regmap_gate { > + struct rtk_clk_regmap clkr; > + unsigned int gate_ofs; > + u8 bit_idx; > + u32 write_en : 1; > +}; > + > +#define __rtk_clk_regmap_gate_hw(_p) __rtk_clk_regmap_hw(&(_p)->clkr) > + > +#define __RTK_CLK_REGMAP_GATE(_name, _parent, _ops, _flags, _ofs, _bit_idx, \ > + _write_en) \ > + struct rtk_clk_regmap_gate _name = { \ > + .clkr.hw.init = CLK_HW_INIT(#_name, _parent, _ops, _flags), \ > + .gate_ofs = _ofs, \ > + .bit_idx = _bit_idx, \ > + .write_en = _write_en, \ > + } > + > +#define RTK_CLK_REGMAP_GATE(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ > + __RTK_CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ops, _flags, _ofs, \ > + _bit_idx, _write_en) > + > +#define RTK_CLK_REGMAP_GATE_RO(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ > + __RTK_CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ro_ops, _flags, \ > + _ofs, _bit_idx, _write_en) > + > +#define __RTK_CLK_REGMAP_GATE_NO_PARENT(_name, _ops, _flags, _ofs, _bit_idx, \ > + _write_en) \ > + struct rtk_clk_regmap_gate _name = { \ > + .clkr.hw.init = CLK_HW_INIT_NO_PARENT(#_name, _ops, _flags), \ > + .gate_ofs = _ofs, \ > + .bit_idx = _bit_idx, \ > + .write_en = _write_en, \ > + } > + > +#define RTK_CLK_REGMAP_GATE_NO_PARENT(_name, _flags, _ofs, _bit_idx, _write_en) \ > + __RTK_CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ops, _flags, _ofs, \ > + _bit_idx, _write_en) > + > +#define RTK_CLK_REGMAP_GATE_NO_PARENT_RO(_name, _flags, _ofs, _bit_idx, _write_en) \ > + __RTK_CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ro_ops, _flags, \ > + _ofs, _bit_idx, _write_en) > + > +static inline struct rtk_clk_regmap_gate *to_rtk_clk_regmap_gate(struct clk_hw *hw) > +{ > + struct rtk_clk_regmap *clkr = to_rtk_clk_regmap(hw); > + > + return container_of(clkr, struct rtk_clk_regmap_gate, clkr); > +} > + > +extern const struct clk_ops rtk_clk_regmap_gate_ops; > +extern const struct clk_ops rtk_clk_regmap_gate_ro_ops; > + > +#endif /* __CLK_REALTEK_CLK_REGMAP_GATE_H */ > -- > 2.43.0 > >