From: Will Deacon <will@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
Fuad Tabba <fuad.tabba@linux.dev>
Cc: mark.rutland@arm.com, kernel-team@android.com,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Rob Herring <robh@kernel.org>,
James Clark <james.clark@linaro.org>,
Jonathan Corbet <corbet@lwn.net>,
Randy Dunlap <rdunlap@infradead.org>,
Shuah Khan <skhan@linuxfoundation.org>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] arm64/boot: Disable trapping of PMZR_EL0 writes to EL2
Date: Wed, 23 Sep 2026 14:00:05 +0100 [thread overview]
Message-ID: <179016687079.3278822.12341361045842371613.b4-ty@kernel.org> (raw)
In-Reply-To: <20260922181430.3532371-1-fuad.tabba@linux.dev>
On Tue, 22 Sep 2026 19:14:30 +0100, Fuad Tabba wrote:
> __init_el2_fgt2() writes one mask to both HDFGRTR2_EL2 and HDFGWTR2_EL2.
> PMZR_EL0 is write-only, so its trap bit, nPMZR_EL0, exists only in
> HDFGWTR2_EL2 and is therefore never set: a PMZR_EL0 write from the host
> traps to EL2, where the nVHE hypervisor has no handler and BUG()s. The
> kernel never writes PMZR_EL0, but kernel.perf_user_access=1 has the PMU
> driver set PMUSERENR_EL0.UEN for a task with a user-read event, so a
> write from EL0 reaches the trap and takes the host down without a panic
> message.
>
> [...]
Applied to arm64 (for-next/fixes), thanks!
[1/1] arm64/boot: Disable trapping of PMZR_EL0 writes to EL2
https://git.kernel.org/arm64/c/2bc6b218717b
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
prev parent reply other threads:[~2026-09-23 13:00 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-22 18:14 Fuad Tabba
2026-09-22 19:47 ` Oliver Upton
2026-09-22 21:09 ` Fuad Tabba
2026-09-22 22:31 ` Oliver Upton
2026-09-23 6:37 ` Anshuman Khandual
2026-09-23 13:00 ` Will Deacon [this message]
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