Re: [PATCH net-next 04/11] docs: networking: Document IPQ5424 as a supported SoC

[netdev-bot+sashiko@kernel.org]

Thank you for your contribution! Sashiko AI review found more severe
issue(s) in other patches of this series. This mail is only an FYI, in case
you want to address the nit picks below when you respin.

Low priority / nit picks for your consideration:

- [Low] At this commit ("docs: networking: Document IPQ5424 as a
  supported SoC"), ppe.rst lists IPQ5424 as supported by the PPE driver,…

--

docs: networking: Document IPQ5424 as a supported SoC

This commit updates the Qualcomm PPE driver documentation to add IPQ5424
to the list of supported SoCs. It also describes how the PPE hardware
differs between SoCs: clock rate, front panel ports and FIFO interfaces.

> diff --git a/Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst b/Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst
> index 4ab299a28969a..04c48cec66d53 100644
> --- a/Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst
> +++ b/Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst
> @@ -167,6 +167,14 @@ PPE Driver Supported SoCs
>  The PPE driver supports the following IPQ SoC:
>  
>  - IPQ9574
> +    The PPE runs at a clock rate of 353 MHz. The switch core has 6 front panel
> +    ports (port1 to port6) and two FIFO interfaces: the EDMA FIFO (port0) for
> +    the host CPU communication and the EIP FIFO (port7) for the EIP engine.
> +- IPQ5424
> +    The PPE reuses the same switch core as IPQ9574 and runs at a clock rate of
> +    375 MHz. It supports 3 front panel ports (port1 to port3) with MAC0 to MAC2,
> +    and only the EDMA FIFO interface (port0) for the host CPU communication. The
> +    EIP FIFO and port4 to port6 are not available.

[Severity: Low]
This isn't a bug, but should this patch go after the driver patches in the
series? At this commit the driver does not support IPQ5424 yet.

In drivers/net/ethernet/qualcomm/ppe/ppe.c, qcom_ppe_of_match[] still has
only the IPQ9574 compatible:

    { .compatible = "qcom,ipq9574-ppe" },

The clock rate and port count are also fixed to the IPQ9574 values, and
qcom_ppe_probe() applies them unconditionally:

    #define PPE_PORT_MAX		8
    #define PPE_CLK_RATE		353000000
    ...
    ppe_dev->clk_rate = PPE_CLK_RATE;
    ppe_dev->num_ports = PPE_PORT_MAX;

At this commit, ppe_icc_data[] has only the IPQ9574 interconnect paths.
In ppe_config.c, ipq9574_ppe_bm_port_config also still includes the EIP
BM port.

Later patches in the series close this gap:

- "net: ethernet: qualcomm: ppe: Add platform support for IPQ5424" adds
  struct ppe_of_data, IPQ5424_PPE_CLK_RATE (375000000),
  IPQ5424_PPE_PORT_MAX (4), ipq5424_ppe_icc_data and the
  "qcom,ipq5424-ppe" match entry.
- "net: ethernet: qualcomm: ppe: Add IPQ5424 BM buffer configuration"
  adds ipq5424_ppe_bm_port_config.

The ppe.rst text does not change by the end of the series and matches the
final driver. The only concern is that, when bisecting to this commit,
the documentation lists support that does not exist yet.

>  
>  
>  Enabling the Driver

-- 
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20261008-qcom_ipq5424_ppe-v1-0-16caf43e44ee%40oss.qualcomm.com