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[91.210.24.215]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5bcdde36114sm3388236e87.1.2026.10.13.00.10.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 00:10:24 -0700 (PDT) From: Fil Dunsky To: Conor Dooley Cc: Thomas Gleixner , Radu Rendec , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Andi Shyti , Wim Van Sebroeck , Guenter Roeck , Russell King , Arnd Bergmann , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: Re: [PATCH 00/11] Cortina Systems CS75xx: interrupt controller, GPIO, I2C and TWD watchdog In-Reply-To: <20261012-dreamlike-hazily-19bb60326f0a@spud> References: <20261012-b4-cs75xx-s2-v1-0-8a7641b7b79c@gmail.com> <20261012-dreamlike-hazily-19bb60326f0a@spud> Date: Tue, 13 Oct 2026 10:10:22 +0300 Message-ID: <179187542217.3247897.4323160442877168450@gmail.com> Content-Transfer-Encoding: 8bit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format="fixed" Hi Conor, Sorry for the late reply, and for sending v2 and v3 without addressing this - I missed your mail. On Mon, Oct 12, 2026 at 07:48:00PM +0100, Conor Dooley wrote: > I think what's here looks really suspect - regions of two registers > wide, interlaced between devices etc. > You mention syscons here, and really that's where I think that this > should go. The region at 0xf007_0000 looks exactly like a syscon to me > and should be modelled as one. Understood. The block at 0xf007_0000 is the "peripheral" register block of the vendor kernel: the interrupt status/enable pairs, the UARTs, GPIO banks, the I2C (BIW), SPI, MDIO and timer registers are all packed into it. Would you be fine with a "cortina,cs7542-peripheral", "syscon", "simple-mfd" node covering it, with the interrupt controller as a child node without its own reg that gets a regmap from the parent? The UART, GPIO and I2C nodes would stay separate devices with their own reg, as you suggest below. > I think it's fine to make a GPIO controller at this point, and leave > pinctrl to later, but I don't think that it is acceptable to pretend > that the mux registers are part of the GPIO controller. The pinctrl-less > GPIO controller would have to either rely on something else (e.g. > firmware) setting the mux registers or be not entirely functional until > the pinctrl arrives Agreed. The next version drops the mux register from the GPIO binding and driver and relies on the boot loader's pin mux. A line that the boot loader leaves muxed to a peripheral then stays unusable as a GPIO until the pin controller exists; I will check which of the Almond+ lines (reset button, touchscreen interrupt) that affects before sending, and leave those out of the dts if needed. I will not send it before the interrupt controller question is settled, and not before 48 hours have passed in any case. Thanks, Fil