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XilSEM runs as part of the Platform Loader and Manager (PLM) on the PMC and detects (and optionally corrects) soft errors in Versal Configuration Memory, notifying error events to user applications. The new compatible string only needs a single register region and does not use reg-names or interrupts, so the schema gates these requirements per compatible string. Signed-off-by: Rama devi Veggalam --- Changes in v4: - Added a new "xlnx,versal-xilsem" compatible string to the existing xlnx,versal-ddrmc-edac.yaml binding, gated via allOf/if-then so DDRMC and XilSEM requirements (reg, reg-names, interrupts) are validated independently per compatible string. Changes in v3: - Merged XilSEM edac with Versal Edac Changes in v2: - Changed "xlnx,versal-xilsem-edac" to constant - Removed "compatible: in required section - Removed "|" in description - Removed "items" in compatible - Fixed indentation in examples - Updated title and description --- .../memory-controllers/xlnx,versal-ddrmc-edac.yaml | 64 +++++++++++++++++++--- 1 file changed, 57 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml index 12f8e9f..b5dc320 100644 --- a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml @@ -4,25 +4,35 @@ $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) and XilSEM EDAC maintainers: - Shubhrajyoti Datta - Sai Krishna Potthuri + - Rama Devi Veggalam description: The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ 4X memory interfaces. Versal DDR memory controller has an optional ECC support which correct single bit ECC errors and detect double bit ECC errors. + Xilinx Versal Soft Error Mitigation (XilSEM) is part of the Platform Loader + and Manager (PLM) which is loaded into and runs on the Platform Management + Controller (PMC). XilSEM is responsible for detecting and optionally + correcting soft errors in Configuration Memory of Versal. Whenever an error + is detected, be it correctable or uncorrectable, XilSEM notifies the errors + to user applications via the firmware's event notification interface, + rather than a devicetree-described interrupt. + properties: compatible: - const: xlnx,versal-ddrmc + enum: + - xlnx,versal-ddrmc + - xlnx,versal-xilsem reg: - items: - - description: DDR Memory Controller registers - - description: NOC registers corresponding to DDR Memory Controller + minItems: 1 + maxItems: 2 reg-names: items: @@ -35,8 +45,39 @@ properties: required: - compatible - reg - - reg-names - - interrupts + +allOf: + - if: + properties: + compatible: + contains: + const: xlnx,versal-ddrmc + then: + properties: + reg: + items: + - description: DDR Memory Controller registers + - description: NOC registers corresponding to DDR Memory Controller + reg-names: + items: + - const: base + - const: noc + required: + - reg-names + - interrupts + + - if: + properties: + compatible: + contains: + const: xlnx,versal-xilsem + then: + properties: + reg: + items: + - description: XilSEM (Soft Error Mitigation) register region + reg-names: false + interrupts: false additionalProperties: false @@ -55,3 +96,12 @@ examples: interrupts = ; }; }; + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + edac@f2014050 { + compatible = "xlnx,versal-xilsem"; + reg = <0x0 0xf2014050 0x0 0xc4>; + }; + }; -- 1.9.5