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Wed, 21 Oct 2026 06:22:39 -0700 Received: from nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Wed, 21 Oct 2026 06:22:38 -0700 Date: Tue, 18 Aug 2026 14:56:25 +0000 Subject: [PATCH 5/5] spi: tegra114: Keep software CS across bus-locked messages From: Vishwaroop A Message-ID: <179258895296.403962.15154108155666791213@nvidia.com> In-Reply-To: <179258895296.403962.3492255118456900623@nvidia.com> References: <179258895296.403962.3492255118456900623@nvidia.com> To: Mark Brown , CC: Laxman Dewangan , Thierry Reding , Jonathan Hunter , "Sowjanya Komatineni" , Rhyland Klein , Suresh Mangipudi , Krishna Yarlagadda , Vishwaroop A , , X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00018545:EE_|MW5PR12MB5681:EE_ X-MS-Office365-Filtering-Correlation-Id: 93f974e2-32e9-42e7-39b9-08df2f766f40 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|376014|36860700016|82310400026|56012099006|261009223327099003|261009221727099003|261009221227099003|11063799006|261009220027099003|261009223027099003|10067099003|22082099003|18002099003|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8TUuZAoVUM1UhMW6mTyfWDRaLhNg5Y7TMcSH+33KbRIvWKVINcQVr9GNNtJyq/DbqwN9WuL47bnTpjSSUEcBFov7LKyEG8qWkjio8JhR+h+fY7GPyYLc9YqawaFMaEw5re5gMgxuoDgHk7yo27Z5v/vASQcYtO367CVN3KCRXr1RWNRMcngZ0VgudAVhdm+zwaLGdRYMsq3LL0sKNEEkntdDmSZdCQoAIh9SpokvS7P3ZTnPnHNkNcpGQfx0OG9xBJpfUwcY5NbmOzVpEZa9gP/ibMPQMciPDOiO1M2ZN0XxRYln+qbaMR9ly0J3egTguSdo5LU5YEPdRfPbkoE3yrsswTbpSEAaBU9dfzye8ZEr6lE0MBCmGjOCrxpM8P3s9la0jeqUA/dcgxQbfJh6fUsPUbGWXyfpBF+wGzoMI+R16f7gMaOMRjRNE1ycUCsE X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2026 13:23:02.7218 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93f974e2-32e9-42e7-39b9-08df2f766f40 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00018545.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5681 A client may hold CS across multiple spi_message submissions under spi_bus_lock() by setting cs_change=1 on the last transfer. The driver records that device in tspi->cs_control so the next message inherits the held-CS state. When CS is controlled by hardware (i.e. for single transfers with cs_change=0), the controller drops CS while it waits for the next packet, which breaks protocols such as TCG TIS-SPI that must keep CS low from command through flow-control polling to the data phase. Keep software CS when cs_control matches the current device, and build COMMAND1 from the running command1_reg rather than def_command1_reg so SPI_CS_SW_HW and SPI_CS_SW_VAL are inherited instead of recomputed. The COMMAND1 write in start_transfer_one() then updates bit length, mode, LSB-first and 3-wire for the new transfer while leaving the asserted CS untouched. Fixes: 1bf9f3c9232d ("spi: tegra114: add support for hw based cs") Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra114.c | 69 +++++++++++++++++++++++++------------- 1 file changed, 46 insertions(+), 23 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 389dcdf15923..14e506374aed 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -779,6 +779,7 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, u32 command1, command2; int req_mode; u32 tx_tap = 0, rx_tap = 0; + bool keep_cs; if (speed != tspi->cur_speed) { clk_set_rate(tspi->clk, speed); @@ -794,7 +795,17 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, if (is_first_of_msg) { tegra_spi_clear_status(tspi); - command1 = tspi->def_command1_reg; + /* + * If the previous message left CS asserted (cs_change=1 + * on its last transfer, e.g. across a bus-locked group), + * start from the current SPI_COMMAND1 value so the + * software CS bits are inherited as-is. Otherwise start + * from the reset default and program CS below. + */ + keep_cs = (tspi->cs_control == spi); + command1 = keep_cs ? tspi->command1_reg : tspi->def_command1_reg; + + command1 &= ~SPI_BIT_LENGTH(~0); command1 |= SPI_BIT_LENGTH(bits_per_word - 1); command1 &= ~SPI_CONTROL_MODE_MASK; @@ -818,28 +829,35 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, else command1 &= ~SPI_BIDIROE; - if (tspi->cs_control) { - if (tspi->cs_control != spi) - tegra_spi_writel(tspi, command1, SPI_COMMAND1); - tspi->cs_control = NULL; - } else + if (keep_cs) { + /* + * CS is already asserted and the CS bits above + * were inherited from command1_reg, so the + * SPI_COMMAND1 write in start_transfer_one() will + * update bit length / mode / LSB / BIDIROE for + * this transfer while leaving CS untouched. + */ + tspi->use_hw_based_cs = false; + } else { tegra_spi_writel(tspi, command1, SPI_COMMAND1); - /* GPIO based chip select control */ - if (spi_get_csgpiod(spi, 0)) - gpiod_set_value(spi_get_csgpiod(spi, 0), 1); + /* GPIO based chip select control */ + if (spi_get_csgpiod(spi, 0)) + gpiod_set_value(spi_get_csgpiod(spi, 0), 1); - if (use_hw_cs) { - tspi->use_hw_based_cs = true; - command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL); - } else { - tspi->use_hw_based_cs = false; - command1 |= SPI_CS_SW_HW; - if (spi->mode & SPI_CS_HIGH) - command1 |= SPI_CS_SW_VAL; - else - command1 &= ~SPI_CS_SW_VAL; + if (use_hw_cs) { + tspi->use_hw_based_cs = true; + command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL); + } else { + tspi->use_hw_based_cs = false; + command1 |= SPI_CS_SW_HW; + if (spi->mode & SPI_CS_HIGH) + command1 |= SPI_CS_SW_VAL; + else + command1 &= ~SPI_CS_SW_VAL; + } } + tspi->cs_control = NULL; if (tspi->last_used_cs != spi_get_chipselect(spi, 0)) { if (cdata && cdata->tx_clk_tap_delay) @@ -1045,11 +1063,16 @@ static int tegra_spi_transfer_one_message(struct spi_controller *host, /* * Use hardware CS only for a single-transfer message with - * cs_change=0. The controller treats each programmed packet as - * a separate transaction and would pulse CS between transfers of - * a multi-transfer message. + * cs_change=0, and only when CS is not already held from a + * previous message (cs_control == spi). Switching to hardware + * CS while CS is held would release it between packets, which + * breaks bus-locked sequences such as TPM TIS-SPI. + * + * Any multi-transfer message must use software CS: the + * controller treats each programmed packet as a separate + * transaction and would pulse CS between transfers. */ - if (list_is_singular(&msg->transfers)) { + if (tspi->cs_control != spi && list_is_singular(&msg->transfers)) { xfer = list_first_entry(&msg->transfers, struct spi_transfer, transfer_list); use_hw_cs = !xfer->cs_change; -- 2.17.1