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Wed, 21 Oct 2026 06:22:34 -0700 Received: from nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Wed, 21 Oct 2026 06:22:33 -0700 Date: Wed, 21 Oct 2026 10:14:06 +0000 Subject: [PATCH 0/5] spi: tegra114: chip-select fixes and PIO-only probe From: Vishwaroop A Message-ID: <179258895296.403962.3492255118456900623@nvidia.com> To: Mark Brown , CC: Laxman Dewangan , Thierry Reding , Jonathan Hunter , "Sowjanya Komatineni" , Rhyland Klein , Suresh Mangipudi , Krishna Yarlagadda , Vishwaroop A , , X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0001854C:EE_|LV8PR12MB9419:EE_ X-MS-Office365-Filtering-Correlation-Id: 40acc64b-3202-4f69-5d54-08df2f766bc2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|82310400026|1800799024|23010399003|18002099003|10067099003|260925021911599003|261009221727099003|260925021311599003|261009223027099003|261009221227099003|11063799006|261009223327099003|261009220027099003|260925022911599003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ae92MZOTY1PY27Btb72xRQ8jsUf9p/KbCefDBWeY1gSW7menS85VB7taMAVKDEzfZg6iaIKG6W96MDBhf1yYvbhKB1dTjrlXo8EslDuwDg0INY7QTi45klZFgaW5xqP4+dmG+qX3sBc74S+895KyMTfzW3iyb1IvTiO6iNy3cjMw8uph1faslueEWrQXEnpybti2meDCEsrGFmacwaVch1381bz4l/minqhcnWYodoeEly1HfmRR2frxNcyDFnN3NKFFNURQGQcDU61DiZ7oCgu9+HoIUE3ht3vuEqL5gbj+CY6lajdx1ld+eo5Ei041rpFfzXEBZ3sDIzAZUsbPDW8J5UdYyrKkMwc91+L1sDnCoGdBJ6tifisShuzGns94PeJjVldegj5E5ZdQPNThfycsIt4xyBfOYPy+ZcQelS6wy0PYwj4po6zPRa84iT1e X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2026 13:22:56.8678 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40acc64b-3202-4f69-5d54-08df2f766bc2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0001854C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9419 Tegra114 SPI sends each transfer as its own packet, and hardware CS follows that packet. The driver implements transfer_one_message(), so it has to do the per-transfer delay and cs_change itself. It gets both wrong. The delay runs after CS is dropped. A mid-message cs_change drops CS and never drives it active again. When the last transfer holds CS, the next message can turn hardware CS back on and drop the line. TIS-SPI under spi_bus_lock() needs CS held across those messages. Multi-transfer messages already use software CS; patch 4 only moves that choice so patch 5 can keep it. Patch 1 is separate. A missing "dmas" property fails probe even though PIO works, so fall back to PIO. Krishna Yarlagadda (1): spi: tegra114: Allow PIO fallback when DMA is unavailable Vishwaroop A (4): spi: tegra114: Run per-transfer delay before ending the transfer spi: tegra114: Assert CS between transfers when cs_change is set spi: tegra114: Decide the chip-select mode once per message spi: tegra114: Keep software CS across bus-locked messages drivers/spi/spi-tegra114.c | 126 ++++++++++++++++++++++++++----------- 1 file changed, 89 insertions(+), 37 deletions(-) base-commit: b810335a0699d1810683796b0e3ffe8827ddfe6c -- 2.17.1