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Sun, 25 Oct 2026 08:24:30 -0700 (PDT) Received: from [127.0.1.1] ([2001:861:39c2:e340:4c3:3a00:d533:9d50]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a35a04ae28sm132982575e9.2.2026.10.25.08.24.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Oct 2026 08:24:30 -0700 (PDT) From: Romain TISSERAND To: sashiko-reviews@lists.linux.dev Cc: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Heiko Stuebner , Liu Ying , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drm/bridge: dw-mipi-dsi: use the lane rate for lbcc when lanes run faster Date: Sun, 25 Oct 2026 16:24:29 +0100 Message-ID: <179294186960.4141843.10824416552753869438@gmail.com> In-Reply-To: References: <20261025142639.3454322-1-romain.tisserand@gmail.com> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 On Sun, 25 Oct 2026 14:38:50 +0000, sashiko-bot@kernel.org wrote: > For a 4-lane non-burst panel using MIPI_DSI_FMT_RGB666_PACKED (bpp = 18), > (bpp / lanes) truncates from 4.5 to 4, giving a lane rate of 5 * mpclk Mbps. > That is only 11.1% (1/9) above the 4.5 * mode->clock pixel bandwidth, rather > than 25%. [...] > If the slack is only meant to ignore lane_mbps being rounded up to the next > MHz, should the check compare dsi->lane_mbps against > DIV_ROUND_UP_ULL(pixel_kbps, MSEC_PER_SEC) instead of adding pixel_kbps / 8? Right, the 1/8 slack misses that case. v2 will use the lane rate when lane_mbps is above the pixel bandwidth rounded up to the next MHz, which keeps i.MX93, Meson and STM in non-burst mode on the pixel clock formula. > Should pixel_kbps and the pixel-clock lbcc calculation divide by > dw_mipi_dsi_get_lanes(dsi) instead of dsi->lanes to handle dual-DSI panels? With dsi->lanes the patch doesn't change the timing of the dual-DSI Gru Scarlet panel: its lane rate stays below the per-link pixel bandwidth, so it keeps the current computation. Switching to the total lane count would change that timing, and I can't test it, so I'll keep dsi->lanes in this patch and leave the dual-DSI accounting to a separate one. I'll send v2 in about a week. Romain