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[159.112.31.107]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-91ca807047bsm44369856d6.39.2026.10.31.09.24.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Oct 2026 09:24:32 -0700 (PDT) From: Christian Cortner To: Konrad Dybcio , Bjorn Andersson , Vinod Koul , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] phy: qcom: edp: update v8 power-on programming sequence Date: Sat, 31 Oct 2026 11:24:31 -0500 Message-ID: <179346367993.44447.8683103034067826560.x2e-share-edp@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: References: <20260622-glymur-edp-phy-v1-0-814b45089ac9@oss.qualcomm.com> <20260622-glymur-edp-phy-v1-2-814b45089ac9@oss.qualcomm.com> Content-Type: text/plain; charset="us-ascii" X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Konrad, Bjorn, On the Asus Zenbook A16 (glymur, eDP at 5.4 Gbps), this series with Konrad's TXn_LDO_CONFIG value (0x91) fell back to 2 lanes on 14 of 120 link enables, with bit errors on lanes 1 and 3. The firmware ends power-on with five registers set differently: DP_PHY_CFG_1 0x2f -> 0x0f (the bit 5 Konrad flagged) DP_PHY_TX2_TX3_LANE_CTL 0x05 -> 0x00 TXn_RESET_TSYNC_EN 0x0a -> 0x03 DP_PHY_TSYNC_OVRD 0x3e -> 0x10 DP_PHY_CFG after DCC 0x09 -> 0x19 Writing the firmware values at the end of power-on, all 120 enables over two boots trained 4 lanes cleanly, and 10 of 10 resumes. Which register matters is not known. Happy to test a revision. Christian