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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AljSyohj8aXiqrNuukx47QSMrYRBc1Uc6y23+E6aHxJPkxN92J+8qKSV/VZ0N44VxBSajtAd/YnVMbu4U4XpFFKp72gVlu6jq1F1TUYMZJbvYUFz1RadnCAAAJBLx1JaUZPmYp9Z5VNbjGpAxkS20YNf8F0Kw3KeXNf5gu2Et87azCIntS0ODywT+XUk/xXj3WKrPph64y1BZhkPxLEv/ea/oLtGznS3lG4BzFGk7ZUatwH9JwUAUY2SxJ3Y0aPdCxyZr2zNkcHGXcnIAlSr1CGDTEVR/wpo5UqtBZiK83FOhjZBzsI+gax9hp4iFkstLJfXqyHREJERjs24TWGked+gyjtAIZfOJ2tmHrTr8RUqK3lG7WOrqa11La0Lbt1SauJEPiTZ/sClZITYa68W3xb2aonrj++s+Iry498LL7zqxKlskYpHbBbh8rzuBtnp X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2026 10:00:40.8212 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f89a75b7-0e80-4b0b-9060-08df3fdaa4cb X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E6.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY0PR06MB5427 > Unanswered comments from Sashiko, dropping from DT Patchwork. They sat for five days, that is on me. I am answering both reviews in separate mails; this one is about the binding only. On the overlapping reg windows: the USB30 Type-A DRD RCSU block at 0x091c0000 holds the straps of the two controllers and of their PHYs, interleaved: 0x300 STRAP_PIN0 stream ID USB4 0x304 STRAP_PIN1 stream ID USB5 0x30c STRAP_PIN3 clock enables USB4, USB5 0x314 STRAP_PIN5 awcache/arcache USB4 0x324 STRAP_PIN9 awcache/arcache USB5 0x328 STRAP_PIN10 USB2 PLL USB4 0x400 STRAP_STATUS0 AXI clock state USB4 0x410 STRAP_STATUS4 AXI clock state USB5 USB4 needs 0x314 and 0x400, USB5 needs 0x324 and 0x410, and 0x324 falls between 0x314 and 0x400. There is no contiguous window that covers the registers of one controller without also covering a register of the other, so the overlap is what the hardware looks like, not a shortcut. reg describes the window of the block that this instance's glue lives in, and the instance only touches two words of it: the AXI cache attribute at res->start and the AXI clock status at res->start + 0xec. The driver maps that window with devm_ioremap() rather than devm_platform_ioremap_resource(), so no memory region is requested and the second instance cannot fail with -EBUSY on the first one. That is deliberate, and it is why Sashiko's failure mode does not happen here. I did look for a shape without the overlap: - syscon for the block: you already rejected that in v4 - "If you have here MMIO for some glue over IP block, then it is unlikely to be a syscon." I agree, this is USB glue, not a miscellaneous register set. - a container node with the two controllers as children and their index in the block as reg: of_platform_default_populate() only descends into simple-bus, simple-mfd and isa nodes, and a container with no driver would never have its children instantiated. So v8 keeps the v7 shape. I have it ready and am not posting it before you answer this, so that the next version is final on this point. If you think the overlap should not be described this way, please tell me which shape you want and I will send that instead. The other Sashiko findings are driver bugs and are fixed in v8; they will be answered in the other thread. The PHY series is unchanged. Best regards, Hongliang Yang