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From: Tony Rodriguez <unixpro1970@gmail.com>
To: Stian Halseth <stian@itx.no>, Bjorn Helgaas <bhelgaas@google.com>
Cc: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Andreas Larsson" <andreas@gaisler.com>,
	linux-pci@vger.kernel.org, sparclinux@vger.kernel.org,
	linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: Set supported_speeds in set_pcie_port_type()
Date: Sat, 10 Oct 2026 22:44:52 -0700	[thread overview]
Message-ID: <17a20959-44ed-43e5-8414-201120468f2f@gmail.com> (raw)
In-Reply-To: <20261007131304.309511-1-stian@itx.no>

This patch also works on the Sparc S7-2, the correct x8 link is shown 
instead of unknown.

# dmesg | grep -iE x8 | grep -iE link
[    8.421411] mlx5_core 0001:03:00.0: 63.008 Gb/s available PCIe 
bandwidth (8.0 GT/s PCIe x8 link)
[    9.472465] mlx5_core 0001:03:00.1: 63.008 Gb/s available PCIe 
bandwidth (8.0 GT/s PCIe x8 link)
[   14.734746] mlx4_core 0001:04:00.0: 63.008 Gb/s available PCIe 
bandwidth (8.0 GT/s PCIe x8 link)

Tested-by: Tony Rodriguez <unixpro1970@gmail.com>

On 10/7/26 6:13 AM, Stian Halseth wrote:
> sparc64 and powerpc create PCI devices from the device tree in
> of_create_pci_dev(), which calls set_pcie_port_type() but not
> pci_setup_device(). Since d2bd39c0456b, supported_speeds is only set in
> pci_setup_device(), so it stays 0 for these devices.
> pcie_get_speed_cap() then returns PCI_SPEED_UNKNOWN, max_link_speed
> reads "Unknown", and the failed link retraining quirk passes
> PCI_SPEED_UNKNOWN to pcie_set_target_speed(), which warns on a SPARC
> T7-1:
>
>    WARNING: drivers/pci/pcie/bwctrl.c:125 at pcie_set_target_speed+0x284/0x2e0
>
> Set supported_speeds in set_pcie_port_type(), which all three paths
> call.
>
> Fixes: d2bd39c0456b ("PCI: Store all PCIe Supported Link Speeds")
> Closes: https://github.com/sparclinux/issues/issues/109
> Signed-off-by: Stian Halseth <stian@itx.no>
> ---
> Tested on a SPARC T7-1: before, max_link_speed reads "Unknown" and the
> warning above appears with CONFIG_PCIEPORTBUS; after, all 23 PCIe
> devices report their real speed and the quirk lifts the 2.5GT/s
> restriction without a warning. Not tested on powerpc.
>
>   drivers/pci/probe.c | 5 ++---
>   1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 27008e2ea5afc..52a79b033b069 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -1651,6 +1651,8 @@ void set_pcie_port_type(struct pci_dev *pdev)
>   		pdev->aspm_l1_support = 1;
>   #endif
>   
> +	pdev->supported_speeds = pcie_get_supported_speeds(pdev);
> +
>   	parent = pci_upstream_bridge(pdev);
>   	if (!parent)
>   		return;
> @@ -2074,9 +2076,6 @@ int pci_setup_device(struct pci_dev *dev)
>   
>   	set_pcie_untrusted(dev);
>   
> -	if (pci_is_pcie(dev))
> -		dev->supported_speeds = pcie_get_supported_speeds(dev);
> -
>   	/* "Unknown power state" */
>   	dev->current_state = PCI_UNKNOWN;
>   

      reply	other threads:[~2026-10-11  5:44 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-07 13:13 Stian Halseth
2026-10-11  5:44 ` Tony Rodriguez [this message]

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