mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Vasant Hegde <vasant.hegde@amd.com>
To: Wei Wang <wei.w.wang@hotmail.com>,
	"alex@shazbot.org" <alex@shazbot.org>,
	"jgg@nvidia.com" <jgg@nvidia.com>,
	"suravee.suthikulpanit@amd.com" <suravee.suthikulpanit@amd.com>,
	"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
	"joro@8bytes.org" <joro@8bytes.org>
Cc: "kevin.tian@intel.com" <kevin.tian@intel.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"iommu@lists.linux.dev" <iommu@lists.linux.dev>
Subject: Re: [PATCH v2 1/2] iommu/amd: Add IOMMU_PROT_IE flag for memory encryption
Date: Tue, 11 Nov 2025 10:14:32 +0530	[thread overview]
Message-ID: <17ac6394-78fb-4d8e-857d-9dd5829ac8b4@amd.com> (raw)
In-Reply-To: <SEZPR01MB4399DEBB3B5DA122E075899DDCCFA@SEZPR01MB4399.apcprd01.prod.exchangelabs.com>

Wei,


On 11/11/2025 6:48 AM, Wei Wang wrote:
> On Monday, November 10, 2025 5:55 PM, Vasant Hegde wrote:
>> To: Wei Wang <wei.w.wang@hotmail.com>; alex@shazbot.org;
>> jgg@nvidia.com; suravee.suthikulpanit@amd.com;
>> thomas.lendacky@amd.com; joro@8bytes.org
>> Cc: kevin.tian@intel.com; linux-kernel@vger.kernel.org;
>> iommu@lists.linux.dev
>> Subject: Re: [PATCH v2 1/2] iommu/amd: Add IOMMU_PROT_IE flag for
>> memory encryption
>>
>> Hi Wei,
>>
>> On 11/3/2025 7:30 PM, Wei Wang wrote:
>>> Introduce the IOMMU_PROT_IE flag to allow callers of
>>> iommu_v1_map_pages() to explicitly request memory encryption for
>> specific mappings.
>>>
>>> With SME enabled, the C-bit (encryption bit) in IOMMU page table
>>> entries is now set only when IOMMU_PROT_IE is specified. This provides
>>> fine-grained control over which IOVAs are encrypted through the IOMMU
>>> page tables.
>>>
>>> Current PCIe devices and switches do not interpret the C-bit, so
>>> applying it to MMIO mappings would break PCIe peer‑to‑peer
>>> communication. Update the implementation to restrict C-bit usage to
>> non‑MMIO backed IOVAs.
>>
>> Right. Quote from AMD Programmers Manual Vol2, "any pages
>> corresponding to MMIO addresses must be configured with the C-bit clear."
>>
> 
> Yes, thanks.
> 
>>>
>>> Fixes: 2543a786aa25 ("iommu/amd: Allow the AMD IOMMU to work with
>>> memory encryption")
>>> Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
>>> Signed-off-by: Wei Wang <wei.w.wang@hotmail.com>
>>> --->  drivers/iommu/amd/amd_iommu_types.h | 3 ++-
>>>  drivers/iommu/amd/io_pgtable.c      | 7 +++++--
>>
>> May be apply same fix for io_pgtable_v2.c as well? (Of course filename
>> changed with generic pt series).
> 
> Yes. I was uncertain about the 1st stage mapping as it has a usage for
> GVA->GPA mappings, and for the trusted MMIO case, we do need the
> C-bit added to GPA. But since vIOMMU isn’t supported for SNP guests,
> and the trusted MMIO isn't ready yet, I think it should be safe to proceed
> with this now. The above consideration can be re-visited when the trusted
> MMIO gets landed.

Right. We use v2 (guest) page table to support PASID/PRI in host.

Agree. for now lets fix the v2 page table as well. We will fix it for Secure
vIOMMU when we add support.




> 
> I'll add it in the next version and see if others might have a different
> perspective on this.

Thanks!

-Vasant


  reply	other threads:[~2025-11-11  4:44 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-03 14:00 [PATCH v2 0/2] iommu/amd: Avoid setting C-bit for MMIO addresses Wei Wang
2025-11-03 14:00 ` [PATCH v2 1/2] iommu/amd: Add IOMMU_PROT_IE flag for memory encryption Wei Wang
2025-11-07  1:02   ` Jason Gunthorpe
2025-11-07  2:39     ` Wei Wang
2025-11-10  9:55   ` Vasant Hegde
2025-11-11  1:18     ` Wei Wang
2025-11-11  4:44       ` Vasant Hegde [this message]
2025-11-03 14:00 ` [PATCH v2 2/2] vfio/type1: Set IOMMU_MMIO in dma->prot for MMIO-backed addresses Wei Wang
2025-11-07  1:03   ` Jason Gunthorpe
2025-11-07  2:38     ` Wei Wang
2025-11-07 14:16       ` Jason Gunthorpe
     [not found]         ` <SI2PR01MB4393E04163E5AC9FD45D56EFDCC3A@SI2PR01MB4393.apcprd01.prod.exchangelabs.com>
2025-11-07 15:57           ` Jason Gunthorpe
2025-11-07 16:19             ` Wei Wang
2025-11-07 16:36               ` Jason Gunthorpe
2025-11-07 17:56                 ` Tom Lendacky
2025-11-07 18:32                   ` Jason Gunthorpe
2025-11-07 19:59                     ` Tom Lendacky
2025-11-10  6:28                       ` Wei Wang
2025-11-10  9:55                       ` Vasant Hegde
2025-11-18 14:36                       ` Jason Gunthorpe

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=17ac6394-78fb-4d8e-857d-9dd5829ac8b4@amd.com \
    --to=vasant.hegde@amd.com \
    --cc=alex@shazbot.org \
    --cc=iommu@lists.linux.dev \
    --cc=jgg@nvidia.com \
    --cc=joro@8bytes.org \
    --cc=kevin.tian@intel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=suravee.suthikulpanit@amd.com \
    --cc=thomas.lendacky@amd.com \
    --cc=wei.w.wang@hotmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®