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Sun, 30 Nov 2025 20:15:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IHUvdYqQdcAB8wtQ4iFi6hdrLX7WH1Zr/sDxqFvq3nFRKk9zpvXvS8fz9AvXPWK52opFXU2Cw== X-Received: by 2002:a17:903:1b2b:b0:298:43f4:cc49 with SMTP id d9443c01a7336-29b6c5225f0mr420884085ad.24.1764562502354; Sun, 30 Nov 2025 20:15:02 -0800 (PST) Received: from [192.168.1.9] ([117.211.36.176]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29bce47096csm106669955ad.44.2025.11.30.20.14.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Nov 2025 20:15:02 -0800 (PST) Message-ID: <17b0f475-6c67-4cef-9277-251f45c1837c@oss.qualcomm.com> Date: Mon, 1 Dec 2025 09:44:56 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] drm/msm: Fix a7xx per pipe register programming To: Anna Maniscalco Cc: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20251128-gras_nc_mode_fix-v2-1-634cda7b810f@gmail.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: <20251128-gras_nc_mode_fix-v2-1-634cda7b810f@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: CRL0jBISfYZNeovz2_a8rfuIcP7GUFn9 X-Authority-Analysis: v=2.4 cv=WpYm8Nfv c=1 sm=1 tr=0 ts=692d1647 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=bQZbETVgiEA5ROTFRdaCHA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=ScosPgwaH3TmPZige8AA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: CRL0jBISfYZNeovz2_a8rfuIcP7GUFn9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjAxMDAzMSBTYWx0ZWRfX9gnQGeQJhQhJ Hu+Mq2lv/5tQ0qgcN7bzsoTIyPUodsbQO7GaMOs4ARblyrs0miYIOP+Rfoe93pwHxd19rfW7wRP W66ag2e3L/8+DKRQOey6Ap7nVi/eDcCofNpLl7e1p3Jfrn2Hx33BA6Qm8Zd+sjTlDRYhHHAnCVQ WV2zdclQcaqa1Zt9zr6n+oDalvqz/ohpAsKP22RDis4Bzr4cQrUG5hSnbBzy0j0uYxhXzw/J+cW a9X55/nRRyRLRl2hgBW8f3oF6c86TNSOnknmsoxAeXPdSEqpanWPGyYRvU4GudjAbIpmfU+AtoU 4n8jT52kOTB5jotErBlsW3LmqX4La58TSR5lR8D4MndSyQFC7zC+TvH1v8zB4ZuBENmxbZzb/4R Bx0ewO8JU9wAX6fkMXFSaacLvWbXew== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_08,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 bulkscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512010031 On 11/28/2025 10:47 PM, Anna Maniscalco wrote: > GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe > but it needs to be programmed for both. > > Program both pipes in hw_init and introducea separate reglist for it in > order to add this register to the dynamic reglist which supports > restoring registers per pipe. > > Fixes: 91389b4e3263 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info") > Cc: stable@vger.kernel.org > Signed-off-by: Anna Maniscalco > --- > Changes in v2: > - Added missing Cc: stable to commit > - Added pipe_regs to all 7xx gens > - Null check pipe_regs in a7xx_patch_pwrup_reglist > - Added parentheses around bitwise and in a7xx_patch_pwrup_reglist > - Use A7XX_PIPE_{BR, BV, NONE} enum values > - Link to v1: https://lore.kernel.org/r/20251127-gras_nc_mode_fix-v1-1-5c0cf616401f@gmail.com > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 12 ++++++++++- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 34 +++++++++++++++++++++++++++---- > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 ++++++++++++ > 4 files changed, 55 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 29107b362346..10732062d681 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -1376,7 +1376,6 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = { > REG_A6XX_UCHE_MODE_CNTL, > REG_A6XX_RB_NC_MODE_CNTL, > REG_A6XX_RB_CMP_DBG_ECO_CNTL, > - REG_A7XX_GRAS_NC_MODE_CNTL, > REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, > REG_A6XX_UCHE_GBIF_GX_CONFIG, > REG_A6XX_UCHE_CLIENT_PF, > @@ -1448,6 +1447,12 @@ static const u32 a750_ifpc_reglist_regs[] = { > > DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist); > > +static const struct adreno_reglist_pipe a7xx_reglist_pipe_regs[] = { > + { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, > +}; > + > +DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_reglist_pipe); > + > static const struct adreno_info a7xx_gpus[] = { > { > .chip_ids = ADRENO_CHIP_IDS(0x07000200), > @@ -1491,6 +1496,7 @@ static const struct adreno_info a7xx_gpus[] = { > .hwcg = a730_hwcg, > .protect = &a730_protect, > .pwrup_reglist = &a7xx_pwrup_reglist, > + .pipe_reglist = &a7xx_reglist_pipe, > .gbif_cx = a640_gbif, > .gmu_cgc_mode = 0x00020000, > }, > @@ -1513,6 +1519,7 @@ static const struct adreno_info a7xx_gpus[] = { > .hwcg = a740_hwcg, > .protect = &a730_protect, > .pwrup_reglist = &a7xx_pwrup_reglist, > + .pipe_reglist = &a7xx_reglist_pipe, > .gbif_cx = a640_gbif, > .gmu_chipid = 0x7020100, > .gmu_cgc_mode = 0x00020202, > @@ -1548,6 +1555,7 @@ static const struct adreno_info a7xx_gpus[] = { > .protect = &a730_protect, > .pwrup_reglist = &a7xx_pwrup_reglist, > .ifpc_reglist = &a750_ifpc_reglist, > + .pipe_reglist = &a7xx_reglist_pipe, > .gbif_cx = a640_gbif, > .gmu_chipid = 0x7050001, > .gmu_cgc_mode = 0x00020202, > @@ -1590,6 +1598,7 @@ static const struct adreno_info a7xx_gpus[] = { > .protect = &a730_protect, > .pwrup_reglist = &a7xx_pwrup_reglist, > .ifpc_reglist = &a750_ifpc_reglist, > + .pipe_reglist = &a7xx_reglist_pipe, > .gbif_cx = a640_gbif, > .gmu_chipid = 0x7090100, > .gmu_cgc_mode = 0x00020202, > @@ -1623,6 +1632,7 @@ static const struct adreno_info a7xx_gpus[] = { > .hwcg = a740_hwcg, > .protect = &a730_protect, > .pwrup_reglist = &a7xx_pwrup_reglist, > + .pipe_reglist = &a7xx_reglist_pipe, > .gbif_cx = a640_gbif, > .gmu_chipid = 0x70f0000, > .gmu_cgc_mode = 0x00020222, > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 0200a7e71cdf..422ce4c97f70 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -849,9 +849,16 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) > min_acc_len_64b << 3 | > hbb_lo << 1 | ubwc_mode); > > - if (adreno_is_a7xx(adreno_gpu)) > - gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, > - FIELD_PREP(GENMASK(8, 5), hbb_lo)); > + if (adreno_is_a7xx(adreno_gpu)) { > + for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) { > + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, > + A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id)); > + gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, > + FIELD_PREP(GENMASK(8, 5), hbb_lo)); > + } > + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, > + A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE)); > + } > > gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, > min_acc_len_64b << 23 | hbb_lo << 21); > @@ -865,9 +872,11 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) > struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > const struct adreno_reglist_list *reglist; > + const struct adreno_reglist_pipe_list *pipe_reglist; > void *ptr = a6xx_gpu->pwrup_reglist_ptr; > struct cpu_gpu_lock *lock = ptr; > u32 *dest = (u32 *)&lock->regs[0]; > + u32 pipe_reglist_count = 0; > int i; > > lock->gpu_req = lock->cpu_req = lock->turn = 0; > @@ -907,7 +916,24 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) > * (
), and the length is > * stored as number for triplets in dynamic_list_len. > */ > - lock->dynamic_list_len = 0; > + pipe_reglist = adreno_gpu->info->a6xx->pipe_reglist; > + if (pipe_reglist) { > + for (u32 pipe_id = A7XX_PIPE_BR; pipe_id <= A7XX_PIPE_BV; pipe_id++) { This patch is probably not rebased on msm-next. On msm-next tip, we have removed A7XX prefix for pipe enums. > + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, > + A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id)); > + for (i = 0; i < pipe_reglist->count; i++) { > + if ((pipe_reglist->regs[i].pipe & BIT(pipe_id)) == 0) > + continue; > + *dest++ = A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id); > + *dest++ = pipe_reglist->regs[i].offset; > + *dest++ = gpu_read(gpu, pipe_reglist->regs[i].offset); > + pipe_reglist_count++; > + } > + } > + gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, > + A7XX_CP_APERTURE_CNTL_HOST_PIPE(A7XX_PIPE_NONE)); > + } > + lock->dynamic_list_len = pipe_reglist_count; > } > > static int a7xx_preempt_start(struct msm_gpu *gpu) > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > index 6820216ec5fc..0a1d6acbc638 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > @@ -46,6 +46,7 @@ struct a6xx_info { > const struct adreno_protect *protect; > const struct adreno_reglist_list *pwrup_reglist; > const struct adreno_reglist_list *ifpc_reglist; > + const struct adreno_reglist_pipe_list *pipe_reglist; nit: Maybe dyn_pwrup_reglist is a better name. Reviewed-by: Akhil P Oommen -Akhil > const struct adreno_reglist *gbif_cx; > const struct adreno_reglist_pipe *nonctxt_reglist; > u32 max_slices; > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index 0f8d3de97636..1d0145f8b3ec 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -188,6 +188,19 @@ static const struct adreno_reglist_list name = { \ > .count = ARRAY_SIZE(name ## _regs), \ > }; > > +struct adreno_reglist_pipe_list { > + /** @reg: List of register **/ > + const struct adreno_reglist_pipe *regs; > + /** @count: Number of registers in the list **/ > + u32 count; > +}; > + > +#define DECLARE_ADRENO_REGLIST_PIPE_LIST(name) \ > +static const struct adreno_reglist_pipe_list name = { \ > + .regs = name ## _regs, \ > + .count = ARRAY_SIZE(name ## _regs), \ > +}; > + > struct adreno_gpu { > struct msm_gpu base; > const struct adreno_info *info; > > --- > base-commit: 7bc29d5fb6faff2f547323c9ee8d3a0790cd2530 > change-id: 20251126-gras_nc_mode_fix-7224ee506a39 > > Best regards,