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Fri, 04 Oct 2024 18:24:46 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 494IOjui001441 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 4 Oct 2024 18:24:45 GMT Received: from [10.110.70.43] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 11:24:45 -0700 Message-ID: <17db9ffe-4e30-4776-a1f1-6da81cc0fcc2@quicinc.com> Date: Fri, 4 Oct 2024 11:24:44 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] bus/mhi: Switch trace_mhi_gen_tre fields to native endian To: Carl Vanderlip , Manivannan Sadhasivam CC: kernel test robot , Jeffrey Hugo , , , References: <20241004170321.4047492-1-quic_carlv@quicinc.com> Content-Language: en-US From: Mayank Rana In-Reply-To: <20241004170321.4047492-1-quic_carlv@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: th9RbYqWOVEIVoJ_gKtswMOY_tXK0B7g X-Proofpoint-ORIG-GUID: th9RbYqWOVEIVoJ_gKtswMOY_tXK0B7g X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 clxscore=1011 phishscore=0 bulkscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040127 On 10/4/2024 10:03 AM, Carl Vanderlip wrote: > Each of the __field() macros were triggering sparse warnings similar to: > trace.h:87:1: sparse: sparse: cast to restricted __le64 > trace.h:87:1: sparse: sparse: restricted __le64 degrades to integer > trace.h:87:1: sparse: sparse: restricted __le64 degrades to integer > > Change each little endian type to its similarly sized native integer. > Convert inputs into native endian. > > Reported-by: kernel test robot > Closes: https://lore.kernel.org/oe-kbuild-all/202402071859.8qMhgJEQ-lkp@intel.com/ do you want to add Fixes tag as: Fixes: ceeb64f41fe6 ("bus: mhi: host: Add tracing support") > Signed-off-by: Carl Vanderlip > Reviewed-by: Jeffrey Hugo > --- > drivers/bus/mhi/host/trace.h | 25 +++++++++++++------------ > 1 file changed, 13 insertions(+), 12 deletions(-) > > diff --git a/drivers/bus/mhi/host/trace.h b/drivers/bus/mhi/host/trace.h > index 95613c8ebe06..3e0c41777429 100644 > --- a/drivers/bus/mhi/host/trace.h > +++ b/drivers/bus/mhi/host/trace.h > @@ -9,6 +9,7 @@ > #if !defined(_TRACE_EVENT_MHI_HOST_H) || defined(TRACE_HEADER_MULTI_READ) > #define _TRACE_EVENT_MHI_HOST_H > > +#include > #include > #include > #include "../common.h" > @@ -97,18 +98,18 @@ TRACE_EVENT(mhi_gen_tre, > __string(name, mhi_cntrl->mhi_dev->name) > __field(int, ch_num) > __field(void *, wp) > - __field(__le64, tre_ptr) > - __field(__le32, dword0) > - __field(__le32, dword1) > + __field(uint64_t, tre_ptr) > + __field(uint32_t, dword0) > + __field(uint32_t, dword1) > ), > > TP_fast_assign( > __assign_str(name); > __entry->ch_num = mhi_chan->chan; > __entry->wp = mhi_tre; > - __entry->tre_ptr = mhi_tre->ptr; > - __entry->dword0 = mhi_tre->dword[0]; > - __entry->dword1 = mhi_tre->dword[1]; > + __entry->tre_ptr = le64_to_cpu(mhi_tre->ptr); > + __entry->dword0 = le32_to_cpu(mhi_tre->dword[0]); > + __entry->dword1 = le32_to_cpu(mhi_tre->dword[1]); > ), > > TP_printk("%s: Chan: %d TRE: 0x%p TRE buf: 0x%llx DWORD0: 0x%08x DWORD1: 0x%08x\n", > @@ -176,19 +177,19 @@ DECLARE_EVENT_CLASS(mhi_process_event_ring, > > TP_STRUCT__entry( > __string(name, mhi_cntrl->mhi_dev->name) > - __field(__le32, dword0) > - __field(__le32, dword1) > + __field(uint32_t, dword0) > + __field(uint32_t, dword1) > __field(int, state) > - __field(__le64, ptr) > + __field(uint64_t, ptr) > __field(void *, rp) > ), > > TP_fast_assign( > __assign_str(name); > __entry->rp = rp; > - __entry->ptr = rp->ptr; > - __entry->dword0 = rp->dword[0]; > - __entry->dword1 = rp->dword[1]; > + __entry->ptr = le64_to_cpu(rp->ptr); > + __entry->dword0 = le32_to_cpu(rp->dword[0]); > + __entry->dword1 = le32_to_cpu(rp->dword[1]); > __entry->state = MHI_TRE_GET_EV_STATE(rp); > ), > Reviewed-by: Mayank Rana Regards, Mayank