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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a0771c7sm79029166b.26.2025.07.31.02.29.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 31 Jul 2025 02:29:09 -0700 (PDT) Message-ID: <17f19573-d304-4f45-8611-b62a032f33cf@oss.qualcomm.com> Date: Thu, 31 Jul 2025 11:29:07 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock To: Akhil P Oommen , Taniya Das , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20250702-qcs615-mm-cpu-dt-v4-v5-0-df24896cbb26@quicinc.com> <20250702-qcs615-mm-cpu-dt-v4-v5-2-df24896cbb26@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=WvgrMcfv c=1 sm=1 tr=0 ts=688b3768 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=1f7UYZhOQBCSuS8GvGYA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: dTfjg_fSk1Wy4SIgUfe8U7Buj7L-J0_8 X-Proofpoint-GUID: dTfjg_fSk1Wy4SIgUfe8U7Buj7L-J0_8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzMxMDA2NCBTYWx0ZWRfX3y4jgruBgKpk 4Jnoq8Y1WnXs1qwfdqBwGlHvb+eRsrV7OJ7GVWPDH2+kRsKajEqLj2JcAl3P7BpFO/cdTTz7Jyf KJdkZuq47dw4zavD9j1+wpK5SBo3StNHUtGqNX/X/z9DbAcqHt/eXlKco9ELbWewyyNflY6Ors6 uw/u18l8vqJtJL2bvM9nmsTmA2ipRvzj/jumVeAB5JEQSzh1rJK2MoUfKgGc5W4wREznyKZc+Di eULxuEZAuiPIZzMy7F2lAelDy8n8X24SHvY1wk7KNxUuh5imRn3uaEsirlR7X2pFNKl2QRy6a0t wmhWglylATCPD7Tggo2zLt7eDje910gRfaUF1KZ67ukx2/kRK80U5qHQKjVH1IFBa4/pfKmc8OR lgawJ8dvDN1AxNzc7vbTsk1U4bSiGOHJyj9HKMVaTveWz4/jTjlFmF98POCzJwcXd2o0g1yl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-31_01,2025-07-31_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 spamscore=0 mlxscore=0 impostorscore=0 adultscore=0 malwarescore=0 priorityscore=1501 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507310064 On 7/30/25 6:10 PM, Akhil P Oommen wrote: > On 7/30/2025 7:07 PM, Konrad Dybcio wrote: >> On 7/2/25 11:13 AM, Taniya Das wrote: >>> Add support for video, camera, display and gpu clock controller nodes >>> for QCS615 platform. >>> >>> Reviewed-by: Konrad Dybcio >>> Signed-off-by: Taniya Das >>> --- >> >> Bjorn mentioned offline that these controllers should >> probably have power-domains attached to them (perhaps bar >> GPU_CC, that's under discussion..) > > QCS615 has an rgmu which doesn't manage gpucc. So this is a different > case from the other discussion. Are we talking about scaling mx and cx > rail while setting clk rate? Downstream clk driver does that on behalf > of the clients. I suppose you are not talking about that here. This is also relevant, as pmdomain states are propagated up the tree, e.g. if we have: usb@foobar { ... power-domains = <&gcc USB30_GDSC>; }; when someone calls dev_pm_opp_set_level() (or something equivalent like dev_pm_opp_set_rate() with required-opps defined in the table), it will set the performance state of the GDSC (which is a NOP for the GDSC itself), but if we have this hunk: gcc@feedbeef { ... power-domains = <&rpmhpd RPMHPD_CX>; }; RPMHPD_CX will be declared as a parent of all GCC GDSCs and its state will be altered too. See: drivers/pmdomain/core.c : _genpd_set_performance_state() TLDR: clients are responsible for ensuring vdd_levels are set Konrad